The paper introduces a novel idea of interconnect fault detection, localization and identification based on test response compaction. The above-mentioned operations are made at-speed. The testing process has been split into two steps. The first one is the detection step using a short test sequence of little diagnostic resolution. The second step is the localization step by means of a long, full diagnostic resolution sequence and it is made only in the case of the detection of faults in the first step. The final fault identification phase exploits information stored in the signatures. Because the signature is chosen to be 32 bit long aliasing is negligible. The proposed hardware concept is independent of the type of both the detection test sequence and the localization test sequence. The theory given in the paper is illustrated by the simulation results. Moreover the paper proposes to test testing hardware itself what makes the results reliable

The paper proposes the approach of designing CA registers that work as quick pattern generators. A new effective method of setting the initial state of such registers is presented. It is based on switching a n-cell CA register into a concatenation of p CdSR registers (Cellular Automata quasi Shift Register) each containing r cells and connected with characteristic polynomial x'. The resultant characteristic polynomial of such concatenation is p(x)=x/sup n/. Such concatenation of p registers CASR is referred as PCASR. The paper proves the possibility of setting a PCASR to any initial state by n-bit input sequence without the need of switching flip-flops into the D flip-flop mode. Moreover, it has been proven that any input sequence would be repeated at the output of a n-cell PCASR after n-clock cycle delay. Finally an effective procedure of testing PCASR is proposed.

This paper presents a new analytical method for estimating compaction quality, based on the entropy. Maximization of the entropy of the signature results in an increase of compaction quality. The paper studies the influence of the architecture of a compactor on the entropy growth. This approach is suitable for nonlinear compactors, widely known linear feedback shift registers (LFSRs) and the counting compactors, as well. Useful theorems to determine entropy growth during the test have been given and proven. Furthermore, the class of nonlinear compactors based on shift registers named cyclic feedback shift registers (CFSRs), which guarantee the maximal entropy growth and the aliasing probability of 2/sup -n/, is found. It is shown that they are considerably better than the simplest linear compactor (feedback shift register) and in many cases are quite as good as linear compactors (LFSRs) having primitive polynomials. On the opposite side, compactors based on counters are far worse than CFSRs. The family of CFSRs is much greater than the already explored family of LFSRs and some CFSRs require less overhead.>