Demo Data from VLDB 2026 / reviewers in the wild / expert
Eugen Schenfeld
dblp:36/2777
· DBLP profile ↗
16ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 15Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
5 papers |
High-performance computing · 38% Interconnection networks and networks-on-chip · 32% Integrated circuit design · 24% | |
| Software engineering, system software, and programming languages
1 paper |
Programming languages and type systems · 100% |
Topics — the 15 heaviest of 16, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
interconnect |
0.1 | 1 | 2005 | On the Feasibility of Optical Circuit Switching for High Performance Computing Systems · SC 2005 |
Interconnection networks and networks-on-chip › high-speed networks
supercomputer interconnect |
0.1 | 1 | 2005 | On the Feasibility of Optical Circuit Switching for High Performance Computing Systems · SC 2005 |
High-performance computing › supercomputing
supercomputing systems |
0.1 | 1 | 2005 | On the Feasibility of Optical Circuit Switching for High Performance Computing Systems · SC 2005 |
High-performance computing › supercomputing
bluegene/l |
0.0 | 1 | 2002 | An overview of the BlueGene/L Supercomputer · SC 2002 |
High-performance computing
supercomputing |
0.0 | 1 | 2002 | An overview of the BlueGene/L Supercomputer · SC 2002 |
Integrated circuit design
system-on-chip |
0.0 | 1 | 2002 | An overview of the BlueGene/L Supercomputer · SC 2002 |
High-performance computing
collective communication |
0.0 | 1 | 2005 | On the Feasibility of Optical Circuit Switching for High Performance Computing Systems · SC 2005 |
Energy-efficient computing › power management
dynamic voltage and frequency scaling |
0.0 | 1 | 1996 | Analysis of a Control Mechanism for a Variable Speed Processor · IEEE Trans. Computers 1996 |
Interconnection networks and networks-on-chip › graph embedding
network topology embedding |
0.0 | 1 | 1996 | Embedding Classical Communication Topologies in the Scalable OPAM Architecture · IEEE Trans. Parallel Distributed Syst. 1996 |
Interconnection networks and networks-on-chip
graph embedding |
0.0 | 1 | 1995 | Annealed Embeddings of Communication Patterns in an Interconnection Cached Network · IEEE Trans. Parallel Distributed Syst. 1995 |
Interconnection networks and networks-on-chip
reconfigurable network |
0.0 | 1 | 1995 | Annealed Embeddings of Communication Patterns in an Interconnection Cached Network · IEEE Trans. Parallel Distributed Syst. 1995 |
Programming languages and type systems
type systems |
0.0 | 1 | 1992 | Type Matching, Type-Graphs, and the Schanuel Conjecture · ACM Trans. Program. Lang. Syst. 1992 |
Performance modeling and evaluation
queueing models |
0.0 | 1 | 1996 | Analysis of a Control Mechanism for a Variable Speed Processor · IEEE Trans. Computers 1996 |
Interconnection networks and networks-on-chip
communication locality |
0.0 | 1 | 1995 | Annealed Embeddings of Communication Patterns in an Interconnection Cached Network · IEEE Trans. Parallel Distributed Syst. 1995 |
Algorithms and data structures › data structure design › search structures
hashing |
0.0 | 1 | 1992 | Type Matching, Type-Graphs, and the Schanuel Conjecture · ACM Trans. Program. Lang. Syst. 1992 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.1dynamic run-time policies · 0.1compiler techniques · 0.1system architecture design · 0.0performance scaling studies · 0.0schanuel conjecture · 0.0hashing · 0.0topology embedding algorithms · 0.0queueing analysis · 0.0graph contraction · 0.0bang-bang control · 0.0graph embedding · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | Generating synthetic task graphs for simulating stream computing systems
Deepak Ajwani, Shoukat Ali, Kostas Katrinis, Cheng-Hong Li, Alfred Park, John P. Morrison, Eugen Schenfeld |
J. Parallel Distributed Comput. | 7 |
| 2012 | Switching Optically-Connected Memories in a Large-Scale SystemabstractRecent trends in processor and memory systems in large-scale computing systems reveal a new "memory wall" that prompts investigation on alternate main memory organization separating main memory from processors and arranging them in separate ensembles. In this paper, we study the feasibility of transferring data across processors by using the optical interconnection fabric that acts as a bridge between processor and memory ensembles. We propose a memory switching protocol that transfers data across processors without physically moving the data across electrical switches. Such a mechanism allows large-scale data communication across processors through transfer of a few tiny blocks of meta-data. We present detailed techniques for supporting two communication patterns prevalent in any large-scale scientific and data management applications. We present experimental results analyzing the feasibility of memory switching in a wide range of applications, and characterize applications based on the impact of the memory switching on their performance. Abhirup Chakraborty, Eugen Schenfeld, Dilma Da Silva |
IPDPS | 2 |
| 2011 | A Flexible Workload Generator for Simulating Stream Computing SystemsabstractStream computing is an emerging computational model for performing complex operations on and across multi-source, high volume data flows. Given that the deployment of the model has only started, the pool of mature applications employing this model is fairly small, and therefore the availability of workloads for various types of applications is scarce. Thus, there is a need for synthetic generation of large-scale workloads for evaluation of stream computing applications at scale. This paper presents a framework for producing synthetic workloads for stream computing systems. Our framework extends known random graph generation concepts with stream computing specific features, providing researchers with realistic input stream graphs and allowing them to focus on system development, optimization and analysis. Serving the goal of covering a disparity of potential applications, the presented framework exhibits high user-controlled configurability. The produced workloads could be used to drive simulations for performance evaluation and for proof-of-concept prototyping of processing, networking and operating system hardware and software. Deepak Ajwani, Shoukat Ali, Kostas Katrinis, Cheng-Hong Li, Alfred Park, John P. Morrison, Eugen Schenfeld |
MASCOTS | 7 |
| 2011 | Analytical Performance Modeling for Null Message-Based Parallel Discrete Event SimulationabstractThis paper presents a new analytical performance analysis for null message-based parallel discrete event simulation(PDES). Our analysis builds upon the key operation of selecting simulation events for processing in the null message algorithms. The results not only explain the well-known facts of how the look ahead capability of individual simulation processes (called logical processes, or LPs) affect the simulation performance, but also reveals quantitatively how the look ahead, the communication topology, the computation and communication delays, and the flow control mechanism affect the simulation performance. We first show that all of the LPs in a strongly connected component in the communication topology asymptotically progress at the same speed, regardless of their individual characteristics and their share of computation resource. Second, we derive an analytical upper bound on the simulation performance. The derivation shows that the ratio between the sum of the look ahead and the sum of the event processing and communication delays of LPs in a cycle bounds the simulation speed from the above, and the cycle of LPs imposes the tightest upper bound becomes the bottleneck of the simulation. We conduct a series of simulation experiments to empirically validate our findings. Moreover, we show that by using the derived upper bound as an optimization guidance, we improve the partitioning of a simple parallel simulation example and achieve a four times speedup against the same simulation based on a classic min-cut partitioning strategy. Cheng-Hong Li, Alfred Park, Eugen Schenfeld |
MASCOTS | 3 |
| 2005 | On the Feasibility of Optical Circuit Switching for High Performance Computing SystemsabstractThe interconnect plays a key role in both the cost and performance of large-scale HPC systems. The cost of future high-bandwidth electronic interconnects mushrooms due to expensive optical transceivers needed between electronic switches. We describe a potentially cheaper and more power-efficient approach to building high-performance interconnects. Through empirical analysis of HPC applications, we find that the bulk of inter-processor communication (barring collectives) is bounded in degree and changes very slowly or never. Thus we propose a two-network interconnect: An Optical Circuit Switching (OCS) network handling long-lived bulk data transfers, using optical switches; and a secondary lower-bandwidth Electronic Packet Switching (EPS) network. An OCS could be significantly cheaper, as it uses fewer optical transceivers than an electronic network. Collectives and transient communication packets traverse the electronic network. We present compiler techniques and dynamic run-time policies, using this two-network interconnect. Simulation results show that our approach provides high performance at low cost. Kevin J. Barker, Alan F. Benner, Raymond R. Hoare, Adolfy Hoisie, Alex K. Jones, Darren J. Kerbyson, Rami G. Melhem, Ramakrishnan Rajamony, Eugen Schenfeld, Shuyi Shao, Craig B. Stunkel, Peter Walker |
SC | 10 |
| 2002 | Blue Gene/L, a System-On-A-ChipabstractSummary form only given. Large powerful networks coupled to state-of-the-art processors have traditionally dominated supercomputing. As technology advances, this approach is likely to be challenged by a more cost-effective System-On-A-Chip approach, with higher levels of system integration. The scalability of applications to architectures with tens to hundreds of thousands of processors is critical to the success of this approach. Significant progress has been made in mapping numerous compute-intensive applications, many of them grand challenges, to parallel architectures. Applications hoping to efficiently execute on future supercomputers of any architecture must be coded in a manner consistent with an enormous degree of parallelism. The BG/L program is developing a peak nominal 180 TFLOPS (360 TFLOPS for some applications) supercomputer to serve a broad range of science applications. BG/L generalizes QCDOC, the first System-On-A-Chip supercomputer that is expected in 2003. BG/L consists of 65,536 nodes, and contains five integrated networks: a 3D torus, a combining tree, a Gb Ethernet network, barrier/global interrupt network and JTAG. George S. Almási, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, Alina Deutsch, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, Blake G. Fitch, Joseph Gagliano, Alan Gara, Robert S. Germain, Mark Giampapa, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, T. Jamal-Eddine, Gerard V. Kopcsay, Alphonso P. Lanzetta, Derek Lieber, M. Lu, Mark P. Mendell, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Rick A. Rand, Richard D. Regan, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, Sarabjeet Singh, Peilin Song, Burkhard D. Steinmacher-Burow, Karin Strauss, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, J. Brown, Thomas A. Liebsch, A. Schram, G. Ulsh |
CLUSTER | 50 |
| 2002 | An overview of the BlueGene/L SupercomputerabstractThis paper gives an overview of the BlueGene/L Supercomputer. This is a jointly funded research partnership between IBM and the Lawrence Livermore National Laboratory as part of the United States Department of Energy ASCI Advanced Architecture Research Program. Application performance and scaling studies have recently been initiated with partners at a number of academic and government institutions,including the San Diego Supercomputer Center and the California Institute of Technology. This massively parallel system of 65,536 nodes is based on a new architecture that exploits system-on-a-chip technology to deliver target peak processing power of 360 teraFLOPS (trillion floating-point operations per second). The machine is scheduled to be operational in the 2004-2005 time frame, at price/performance and power consumption/performance targets unobtainable with conventional architectures. Narasimha R. Adiga, Gheorghe Almási 0001, George S. Almási, Yariv Aridor, Rajkishore Barik, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Waiman Chan, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, K. M. Desai, Alina Deutsch, Tamar Domany, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, C. Christopher Erway, J. Esch, Blake G. Fitch, Joseph Gagliano, Alan Gara, Rahul Garg 0001, Robert S. Germain, Mark Giampapa, Balaji Gopalsamy, John A. Gunnels, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, R. D. Jackson, T. Jamal-Eddine, Gerard V. Kopcsay, Elie Krevat, Manish P. Kurhekar, Alphonso P. Lanzetta, Derek Lieber, L. K. Liu, M. Lu, Mark P. Mendell, A. Misra, Yosef Moatti, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Adam J. Oliner, Vinayaka Pandit, R. B. Pudota, Rick A. Rand, Richard D. Regan, Bradley Rubin, Albert E. Ruehli, Silvius Vasile Rus, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, M. Sharma, Edi Shmueli, Sarabjeet Singh, Peilin Song, Vijay Srinivasan, Burkhard D. Steinmacher-Burow, Karin Strauss, Christopher W. Surovic, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Arun R. Umamaheshwaran, P. Verma, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, W. Barrett, C. Engel, B. Drehmel, B. Hilgart, D. Hill, F. Kasemkhani, David J. Krolak, Chun-Tao Li 0001, Thomas A. Liebsch, James A. Marcella, A. Muff, A. Okomo, M. Rouse, A. Schram, M. Tubbs, G. Ulsh, Charles D. Wait, J. Wittrup, Myung Bae, Kenneth A. Dockser, Lynn Kissel, Mark K. Seager, Jeffrey S. Vetter, K. Yates |
SC | 74 |
| 1997 | Special Issue on Parallel Computing with Optical Interconnects
Mary Mehrnoosh Eshaghian-Wilner, Eugen Schenfeld |
J. Parallel Distributed Comput. | 2 |
| 1996 | Multi-Dimensional Locks with Online AllocationabstractSynchronization is inherent to parallel computing and comprises many aspects. One aspect is the access control to shared data, especially important in MIMD shared-memory architectures. Several locking mechanisms have been proposed to perform this task. Most of these schemes rely on very little hardware support, such as atomic read-modify-write operations. Today, the amount of hardware required to implement a locking mechanism is not a major constraint and will be even less important in the future. This makes it interesting to investigate schemes with more flexibility, better performance, and improved ease of use, that rely more on hardware assisted circuits than previous suggestions. In this paper multi-dimensional locking schemes that allocate locks on-line are presented. A lock is assigned to the access control of a data structure only during the time this structure needs to be locked. Three specific schemes are proposed. Two offer the possibility of locking sub-structures within multi-dimensional arrays. All three schemes protect locked structures against accesses of misbehaving threads. Dieter Scheerer, Eugen Schenfeld, Marc A. Viredas |
ICDCS | 2 |
| 1996 | Analysis of a Control Mechanism for a Variable Speed ProcessorabstractOne limitation on the operating speed of electronic circuits is the rate at which the packaging can dissipate heat. In CMOS technology, the heat generated by a processor is approximately proportional to its clock rate. The paper examines the idea of using a variable speed processor (VSP) that can be operated at a high clock speed, and then slowed down to a lower speed before heat accumulation destroys the circuit. Under a workload consisting of bursts of work alternating with idle periods (corresponding to cache misses or other delays), this results in a higher average operating speed. The paper shows the optimality of a bang bang control for the clock rate. It also examines an easier to implement policy that estimates the junction temperature through an upper bound, and uses this to control the clock rate. Closed form expressions are derived for the mean rate of instructions executed by a VSP using each control method. Numerical studies show that both policies give substantial improvements in performance over a single speed processor. Furthermore, the studies suggest that a VSP with a maximum clock rate of 2-4 times that of the single speed processor would suffice to obtain the bulk of the performance improvement. In many cases, the average throughput gain is on the order of 40-60%, without exceeding thermal limits. Arif Merchant, Benjamin Melamed, Eugen Schenfeld, Bhaskar Sengupta |
IEEE Trans. Computers | 3 |
| 1996 | Embedding Classical Communication Topologies in the Scalable OPAM ArchitectureabstractThe paper presents novel embeddings of various classical topologies into the OPAM multicomputer. OPAM consists of a large number of processors that are connected by a two level, crossbar based interconnection network. The network combines a large, optical circuit-switched crossbar (reconfigurable network), with many small, packet-switching crossbars. The necessary embedding is very different than classical approaches. The goal in our case is to minimize routing decisions, so that communication requests can be satisfied by passing through two small crossbars. We show how to map parallel programs to this architecture using graph contraction notations. The family of parallel programs that we consider consists of multiple processes and communication links that are represented by connected, regular graphs such as rings, trees, two dimensional grids, cube connected cycles and hypercubes. In each case we show how to partition the vertex set of the program's graph to subsets, and how to assign each subset a cluster of processors in order to realize the topology of the given problem. In some of the cases we also prove that our partition and assignment algorithms are optimal. Amnon Barak, Eugen Schenfeld |
IEEE Trans. Parallel Distributed Syst. | 2 |
| 1995 | Annealed Embeddings of Communication Patterns in an Interconnection Cached NetworkabstractThe communication needs of many parallel applications exhibit what we call switching locality. In such applications, each computation entity (process, thread, etc.) tends to restrict its communication to a small set of other entities. The physical location or proximity of these entities can be arbitrary, as long as the communication degree is small. The Interconnection Cached Network (ICN) is a reconfigurable network ideally suited for exploiting such locality. The use of fast small crossbar switches (Interconnection Caches) with a larger, but slower, reconfigurable network (optimized for connectivity) lets the ICN adapt to the communication requirements of individual applications, potentially achieving higher performance. Embedding communication patterns efficiently in an ICN, requires finding a bounded l-contraction of the underlying communication graph. The problem of identifying whether a graph has a bounded and l-contraction for a given integer l is known to be NP-complete for l>2. We describe a heuristic algorithm based on simulated annealing for this problem. We test the effectiveness of our approach by using it to embed graphs, representing regular communication patterns, for which the best solutions are deterministically known. The algorithm does not rely on any structural information of the communication pattern and is therefore applicable to irregular patterns as well. The results of applying our heuristics to embed such irregular graphs are also presented. Eugen Schenfeld |
IEEE Trans. Parallel Distributed Syst. | 2 |
| 1994 | A Comparative Performance Study of an Interconnection Cached NetworkabstractThe Holy Grail of multi-computer network architects is an ideal crossbar with large size, high bandwidth and fast switching speed. Currently, only small crossbars with fast switching rates are available. Some technologies, e.g. optics, make it possible to build large, high bandwidth crossbars. However, these crossbars switch slowly. The Interconnection Cached Network (ICN) contains many small crossbars interconnected by a single large crossbar. The large crossbar is used for topology reconfiguration, and the small crossbars for message switching. In many parallel applications, each processing element (PE) communicates with only a small set of other PEs. We call this phenomenon switching locality and show that, in its presence, the ICN performs almost as well as the ideal crossbar. We also show that alternative networks have poorer overall performance in terms of average message latency, highest sustainable throughput, and application scalability. Eugen Schenfeld |
ICPP (1) | 2 |
| 1994 | Parallel Graph Contraction with Applications to a Reconfigurable Parallel ArchitectureabstractCommunication plays a key role in the overall performance of a parallel system. In the general case, the communication network is required to transfer information from any set of sources to to any set of destinations. In practice, parallel applications have various communication needs. Many applications restrict their communication requests to a more limited number of possible connections between sources and destinations. The communication requests of parallel applications are represented by graphs. Parallel graph contraction has been used to embed these graphs into a reconfigurable parallel architecture. We review some of the previous work done in this area showing how various useful communication graphs (e.g., ring, kary trees, mesh, CCC, hypercube, etc.), can be contracted for an efficient embedding. We also present some results for the parallel contraction of other useful graphs such as de Bruijn, shuffle-exchange, mesh of trees, pyramid, and multi-stage communication structures. Lower bounds are proved for all graphs. A heuristic approach for parallel graph contraction is reviewed for irregular graphs based on simulated annealing. Yuh-Dauh Lyuu, Eugen Schenfeld |
ICPP (3) | 2 |
| 1994 | Performance analysis of a synchronous, circuit-switched interconnection cached networkabstractIn many parallel applications, each computation entity (process, thread etc.) switches the bulk of its communication between a small group of other entities. We call this phenomenon switching locality. The Interconnection Cached Network (ICN) is a reconfigurable network especially suited for exploiting switching locality. It consists of many small, fast crossbars interconnected by a large, slow switching crossbar. The large crossbar is used for topology reconfiguration and the smaller crossbars for circuit switching. For a large class of communication patterns displaying switching locality (this includes meshes, tori, trees, rings, pyramids, etc.), it is possible to choose appropriate ICN configurations and assignments of processes to processors such that all communication paths pass through two or less switching components.Much of the previous work on performance analysis of networks has assumed random, uniformly distributed communication and is inapplicable to many real-life parallel applications that lack this uniformity. We develop a methodology to analyze the performance of synchronous, circuit switched networks under different communication traffic patterns. We employ this methodology to study the performance of the ICN in comparison to more popular reconfigurable networks: the delta and the crossbar. We choose two different communication patterns—a 2-D torus representing a high degree of switching locality and a fully connected graph representing complete absence of such locality. We show that in the presence of locality, the ICN comes very close to matching the crossbar's performance. This, together with the shorter network cycle period of the ICN, makes it more desirable. In the absence of switching locality, the reconfigurability of the ICN allows for a graceful degradation in performance. Eugen Schenfeld |
International Conference on Supercomputing | 2 |
| 1992 | Type Matching, Type-Graphs, and the Schanuel ConjectureabstractThis work considers type systems that are defined by type-graphs (tgraphs), which are rooted directed graphs with order among the edges leaving each node. Tgraphs are uniquely mapped into polynomials which, in turn, are each evaluated at a special point to yield an irrational number named the tgraph's magic number . This special point is chosen using the Schanuel conjecture. It is shown that each tgraph can be uniquely represented by this magic number; namely, types are equal if and only if the corresponding magic numbers are equal. Since irrational numbers require infinite precision, the algorithm for generating magic numbers is carried out using a double-precision floating-point approximation. This approximation is viewed as a hashing scheme, mapping the infinite domain of the irrational numbers into finite computer words. The proposed hashing scheme was investigated experimentally, with the conclusion that it is a good and practical hashing method. In tests involving over a million randomly chosen tgraphs, we have not encountered a single collision. We conclude that this method for representation and management of types is practical, and offers novel possibilities for enforcing strict type matching at link time among separately compiled modules. Jacob Katzenelson, Shlomit S. Pinter, Eugen Schenfeld |
ACM Trans. Program. Lang. Syst. | 3 |