Design principles of self checking digital circuits are in the focus of the general interest and many papers exist treating that subject. The use of special data encoding techniques, suitable algorithms of arithmetic, special hardware elements have been proposed long ago. The purpose of this paper is to show that the design can produce rather simple self checking circuit when the design principles are chosen which collaborate harmoniously: 1) decimal numerical system is used 2) decimal digit d ϵ {0, 1, ..., 9} is represented in the Diamond Code by the 5-bit binary number f = 3·d + 2 3) decimal digits' addition algorithm introduced here is simple and effective so that 10 decimal digits can be added in parallel 4) implementation of the addition algorithm by conventional Full Adders results in in a single fault detecting circuit. The design of a decimal adder for 10 decimal numbers, each with 10 digits, is described here as an illustration. It shows the way how to design other decimal arithmetic circuits which are single fault detecting, for instance a multiplier (derived from the adder for 10 decimal numbers).

The testing of LSI chips is expensive and unsatisfactory. On the other hand there are cases (as in space ship computers) where a damaged chip must be localized and replaced. The use of self-checking chips seems to be one of several possible solutions of this problem. The theory of the structure of self-checking logical circuit is covered by literature at least at the fundamental form (see References). However, even when the design principles are supposed to be known, their application to the actual creation of a self-checking circuit of an average complexity is and will remain an art. The reason is quite simple and fundamental: optimization of design criteria (engineering qualifications, performance and physical properties of components of the circuits are entities possessing different physical dimensions — it is impossible to qualify, for instance, two circuits A, B designed for the same task by comparing their speeds and costs if A is faster than B but B is cheaper than A) will never be objective and independent of the talent or whim of the circuit designer. As an example of the design of a self-checking circuit we present here a binary adder (Full Adder) designed under the following considerations: 1: The adder is composed from gates (AND, 0R, NAND, N0R, …). 2: Two level design was chosen. 3. Ripple carry addition was accepted as sufficient simplification for the design experiment. 4. Only two classes of fault were considered: Stuck at ONE, Stuck at ZERO. 5. Any single fault in the circuit must be signalized either during the activity of the circuit (clock ON) or during a test fault injection (clock OFF). 6. The number of cases where a multiple fault remains undetected must be extremely low in comparison with all possible cases. To obtain an adder with all those requirements the following design idea is used: The adder's three bit input (X, Y, C) is transformed into an eight bit signal (S1, i = 0, 1, …, 7) by using ONE FROM EIGHT CODE. This signal, produced by the first level of the circuit, is then transformed by the second level of the circuit into the desired output signal (Z, G) by using four wires and TWO FROM FOUR CODE. Ten fault signals (Fig. 1) are derived from those two codes and checked at the proper state of the clock.

In a logical system with D variables pl, i = 0, 1, ..-, D -1, a functionf is (incompletely) specified by two sets of minterms: p E {Pl ~ containing all minterms which must be present in every canonical ~II-form off, and p E {P}0 containing all minterms excluded from every canonical ~II-form off.Those two sets have no element in common, of course.The membership of any minterm which is neither in [P} ~ nor in [P } 0 is free to be specified later to fulfill prescribed optimization requirements.The function is then called" incompletely specified" and is designated by re.Here the word MINs is used to exclusively designate the MINterms in {P} ~.Expressed in the conventional geometrical model language, MIN designates a point p of the logical space of the system, where fo must be true (f~(p) = 1).Two MINs forming a pair p, p' are called mutually term exclusive iff no term-implicant T off ° exists, which covers them both.A set of MINs is called term ezclusive iff every pair of its elements is composed from hiINs which are mutually term exclusive.It is obvious that for a given fo the number of elements in term exclusive sets has a least upper bound/11.It is shown that M is a lower bound on the number of terms in any Boolean XII-form of fo with other important consequences which permit the development of N-minimal Boolean ZIl-forms under constraints which are much more general than the usual constraint of the minimal count of all literals, which restricts each term of the form to a prime implicant off ~.The solution of the optimal multiple output combinational network is offered as an example of a problem which needs the application of the concept of term exclusiveness. 14.EY WORDS AND PHRASES: Boolean ~II-form,

An algorithmic procedure is presented which produces an optimal two-level multiple-output network. In agreement with procedures suggested by other authors, the set of given (incompletely specified) Boolean functions of variables xi is transformed into a single (mosaic) function f( y,x) by using additional variables yi, related to the structure of the resulting network. The agreement ends here, however. It is shown that the function f(y, x) can be composed in such a way that the following statement can be proven as true.

A processor called Boolean analyzer has been presented at the 1968 IFIP Congress to introduce parallel processing of Boolean expressions [1]. The present paper shows how to increase its speed many times by making its processing more parallel. The applications of the Boolean analyzer are limited to few but important problems. A typical problem of that kind: listing of all implicants of a function of 7 variables defined by not more than 100 term implicants (of the complement of that function) takes only about 40 μs (supposing a delay line storage working at the clock impulse rate of 2.106/s).

A processor called Boolean Analyzer has been presented at IFIP Congress 1968 to introduce parallel processing of Boolean expressions [1]. The present paper shows how to increase its speed many times by making its processing more parallel. The applications of the Boolean Analyzer are limited to few but important problems. A typical problem of that kind: listing of all implicants of a function of 7 variables defined by not more than 100 term implicants (of the complement of that function) takes about 40 microsecond only (supposing a delay line storage working at the clock impulserate of 2.106per sec).

An adder is described for addition of a large number of binary numbers xj, j=1, 2, ⋯, m, where xj=∑ixji⋅ 2i, xji=0, 1, i=0, 1, ⋯, n-1. The adder's algorithm has two parts: 1) the bits xjiare added independently for each binary order i:si=∑jxji≦m and the result expressed in the binary form si=∑kaik, ⋅ 2k, aik=0, 1, k=0, 1,⋯, p-1 (where 2p-1≦mp); 2) the sum y=∑jxjis formed by adding terms sik·2i+kas contributions of the bit sikto the total y. A hardware implementation of this algorithm is suggested where the sum s; is obtained by a sequential circuit which reorders the values xjiso that their sum si, remains unchanged and so that after the reordering the new values xjiiobey the conditions xj+1,i≦xjifor every j=1, 2,⋯, m-1. The implementation with integrated circuits should be quite rewarding because the control of the circuit is done with independent control elements distributed all over the chip.

Addition algorithm, decimal adder with signed digit arithmetic p presented here was designed to establish the following facts: the redundant representation of a decimal digit xi by a 5-bit binary number Xi=3xi leads to a logical design of extreme simplicty; it is possible to form an additional algorithm for the adder so that it can be used to transform numbers written in a conventional decinal form into a signed digit form, and vice versa.

Correspondence between logical relations of Boolean function implicants and numerical relations between identifiers

A system observed from the outside as a black box displays certain activity which can be described (and stored) as variations of the input and output variables of the system during its observation. Such information stored for adequately large intervals of time represents samples of activity ready for statistical analysis. Any time-invariant obtained as a result of this investigation represents an element of behavior of the system which can be explained by the existence of corresponding elements of the internal structure of the black box. The resulting abstract model of the internal structure is algorithmic when the elements of behavior take on the form of a law predicting the future activity from some stored information about the past activity. Not all systems are found to be algorithmic. The activity of any part of an electronic digital system with a central clocking can be defined by Boolean variables arranged in suitable timetables. Any time-invariant Boolean equation holding between these variables represents an element of the system's behavior but does not necessarily contain any algorithmic element of the system. In this paper we show how to make tests of the activity proving the existence of algorithmic elements, their synthesis and the design of corresponding block diagrams of the system.