We study the effect of noise on the classical simulatability of quantum circuits defined by computationally tractable (CT) states and efficiently computable sparse (ECS) operations. Examples of such circuits, which we call CT-ECS circuits, are IQP, Clifford Magic, and conjugated Clifford circuits. This means that there exist various CT-ECS circuits such that their output probability distributions are anti-concentrated and not classically simulatable in the noise-free setting (under plausible assumptions). First, we consider a noise model where a depolarizing channel with an arbitrarily small constant rate is applied to each qubit at the end of computation. We show that, under this noise model, if an approximate value of the noise rate is known, any CT-ECS circuit with an anti-concentrated output probability distribution is classically simulatable. This indicates that the presence of small noise drastically affects the classical simulatability of CT-ECS circuits. Then, we consider an extension of the noise model where the noise rate can vary with each qubit, and provide a similar sufficient condition for classically simulating CT-ECS circuits with anti-concentrated output probability distributions.

Silicon based Physical Unclonable Function (PUF) is a popular security primitive for mitigating such hardware security vulnerabilities. In the recent years, Quasi-adiabatic logic based physical unclonable function (QUALPUF) was proposed. The QUALPUF has ultra low-power consumption, hence it suitable to implement in low-power portable electronic devices. In this paper, we present a new adiabatic PUF which is based on QUALPUF. With improving the circuit topology using a small number of the power supply, the proposed PUF have become compact in size compared with the conventional adiabatic PUF. Through the simulation results, we show that the proposed adiabatic PUF provides higher reliability and lower energy consumption.

We study the computational power of shallow quantum circuits with $O(\log n)$ initialized and $n^{O(1)}$ uninitialized ancillary qubits, where $n$ is the input length and the initial state of the uninitialized ancillary qubits is arbitrary. First, we show that such a circuit can compute any symmetric function on $n$ bits that is classically computable in polynomial time. Then, we regard such a circuit as an oracle and show that a polynomial-time classical algorithm with the oracle can estimate the elements of any unitary matrix corresponding to a constant-depth quantum circuit on $n$ qubits. Since it seems unlikely that these tasks can be done with only $O(\log n)$ initialized ancillary qubits, our results give evidences that adding uninitialized ancillary qubits increases the computational power of shallow quantum circuits with only $O(\log n)$ initialized ancillary qubits. Lastly, to understand the limitations of uninitialized ancillary qubits, we focus on near-logarithmic-depth quantum circuits with them and show the impossibility of computing the parity function on $n$ bits.

Our previously proposed ultra low-power subthreshold adiabatic logic has been a problem that noise margin is reduced, so that it is impossible to implement a cascade connection. In this paper, we propose a novel sub-threshold adiabatic logic. To evaluate our proposed circuit, a half adder, full adder, dynamic flip flop and 4×4 array multiplier are designed, and then the operation function and power dissipation are confirmed. From the simulation results, the power dissipation of the proposed multiplier is lower than that of the conventional CMOS.

This paper presents a measurement result of a bit-parallel multiplier over GF(24) using a secure dual-rail charge-sharing symmetric adiabatic logic. The output functionality and the supply current traces of the fabricated LSI chip are measured in order to analyze the correlation of the current-to-data dependency in respect to the given input signal transitions for resistance against power analysis attack. Furthermore, the verification of the output signals of the LSI chip is measured at dynamic power clock frequency from 0.5-5 MHz.

We study the quantum complexity class QNC0fof quantum operations implement able exactly by constant-depth polynomial-size quantum circuits with unbounded fan-out gates. Our main result is that the quantum OR operation is in QNC0f, which is an affirmative answer to the question of Hoyer and Spalek. In sharp contrast to the strict hierarchy of the classical complexity classes: NC0⊊ AC0⊊ TC0, our result with Hoyer and Spalek's one implies the collapse of the hierarchy of the corresponding quantum ones: QNC0f= QAC0f= QTC0f. Then, we show that there exists a constant-depth sub quadratic-size quantum circuit for the quantum threshold operation. This allows us to obtain a better bound on the size difference between the QNC0fand QTC0fcircuits for implementing the same quantum operation. Lastly, we show that, if the quantum Fourier transform modulo a prime is in QNC0f, there exists a polynomial-time exact classical algorithm for a discrete logarithm problem using a QNC0foracle. This implies that, under a plausible assumption, there exists a classically hard problem that is solvable exactly by a QNC0fcircuit with gates for the quantum Fourier transform.

We investigate our previously proposed charge sharing symmetric adiabatic logic, which was designed to thwart differential power analysis (DPA) attack. The ability of the logic to withstand DPA attacks is analyzed from the variations in the transitional power consumption of individual logics and in the bit-parallel cellular multiplier over GF(2m). Then, we compare the results with those of the previous secure logic styles using the same parameters and under the same conditions. Based on the simulated program with integrated circuit emphasis (SPICE) simulation results, we deduce that our proposed logic is a suitable candidate for secure hardware application in the low-power and low-frequency fields, such as contactless smart card, RFID tags, and wireless sensors.

Multi-Sites Test is the popular way to reduce the cost-of-test (COT) at the wafer and the final test. Limitations exist, however, such as the low Multi-Site Efficiency of analog mixed signal tests and the high system price for large pin count devices. Concurrent Test has been implemented to reduce the test time. This test strategy is difficult to implement without the DFT design of the device. The authors introduced the concept of Multi-Domain Test at VTS 2011 and explained that this Multi-Domain Test solves the aforementioned problems and limitations of Multi-Site Test and Concurrent Test. The authors also showed that the COT of Multi-Domain Test is lower than that of Multi-Site Test for high-end SOC devices. This Multi-Domain Test was applied to a mixed signal SOC. Although the Multi-Site Efficiency of the Dual-Site Test was more than 97%, the COT of the Dual-Domain Test was approximately 10% lower than that of the Dual-Site Test.

The Multi-Domain-Test is the new test strategy to resolve problems and limitations of the Multi-Site-Test and the Concurrent-Test. By this novel test strategy, test time can be reduced down to 50% of the Single-Site-Test with almost the same amount of tester resources. Cost Of Test (COT) can be lower than the Multi-Site-Test that is well used at productions.

This paper presents the simulation results of a 4×4-bit array two phase clocked adiabatic static CMOS logic (2PASCL) multiplier using 0.18 μm standard CMOS technology. We also propose a new design of 2PASCL XOR which reduces the number of transistors as well as the power consumption. Analytical method to compare the lower current flow in adiabatic circuit is also presented. At transition frequencies of 1 to 100 MHz, 4×4-bit array 2PASCL multiplier shows a maximum of 55% reduction in power dissipation to that of a static CMOS. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

We investigate a class QNC/sup 0/ (ADD) that is QNC/sup 0/ with gates for addition of two binary numbers, where QNC/sup 0/ is a class consisting of quantum operations computed by constant-depth quantum circuits. We show that QNC/sup 0/(ADD) = QNC/sup 0/(PAR), where QNC/sup 0/(PAR) is QNC/sup 0/ with Toffoli gates of arbitrary fan-in and gates for parity. Moreover, we show that QNC/sup 0/(ADD) = QAC/sup 0/(MUL) = QAC/sup 0/(DIV), where QAC/sup 0/(MUL) and QAC/sup 0/(DIV) are QNC/sup 0/ with Toffoli gates of arbitrary fan-in and gates for multiplication and division respectively. In the classical setting, similar relationships do not hold. These relationships suggest that QNC/sup 0/ /spl subne/ QNC/sup 0/(ADD); that is, the use of gates for addition increases the computational power of constant-depth quantum circuits. To prove QNC/sup 0/ /spl subne/ QNC/sup 0/(ADD), we present a characterization of this relationship by the one-wayness of a permutation that is constructed explicitly. We conjecture that the permutation is one-way, which implies QNC/sup 0/ /spl subne/ QNC/sup 0/(ADD).

A distributed real-time computer-supported cooperative work (CSCW) platform called the B-ISDN group teleworking system is described. The system combines the high-speed multimedia communication capability with advanced video integrated workstations. The aim of this system is to support ad hoc meetings and real-time collaborative work between small groups of people who are geographically distributed. The main features of the system are face-to-face communication and the capability for sharing and comanipulating shared multimedia information including video. The concept and architecture of the system are described. A prototype group teleworking system that uses B-ISDN multimedia workstations is also described. A mock remote medical consultation application for the system is presented.>