The advantage to "one test at a time" fault diagnosis is its ability to implicate the components of complicated defect behaviors. The disadvantage is the large size and opacity of the diagnostic answer. In this paper, we address the problems of per-test diagnosis by improving the candidate matching, introducing scoring and ranking techniques, and by developing a method to translate the results into common defect scenarios. Our experimental results on simulated defects indicate that not only are the results improved on complex behaviors, but by considering passing test results we improve a common case where per-test algorithms can perform significantly worse than traditional diagnosis algorithms. Finally, our method of candidate analysis provides a way to bridge the per-test approach with traditional model-based fault diagnosis.

The foremost problem in VLSI fault diagnosis is the problem of data: there's simply too much of it. Circuits are large and contain enormous numbers of faults of many types. Full-response fault dictionaries are too large for practical or quick diagnosis, but pass-fail dictionaries often do not provide adequate resolution. The goal of this paper is to examine different sets of diagnostic data, determine the utility of each, and investigate ways of drastically reducing the data requirements for fault diagnosis. In doing so we introduce a new fault signature type, and begin to develop the idea of low-precision fault diagnosis in which useful diagnoses are obtained with a minimum of data and computation.

This paper introduces ELVIS, a custom PLD that solves Boolean satisfiability (SAT) problems and presents a significant improvement over previous approaches. SAT is a core computer science problem with important commercial applications, which include timing verification, automated layout, logic minimization and test pattern generation. ELVIS is the first massively parallel SAT-solver to support efficient loading of formulas and on-line clause addition with no instance-specific placement or routing. Furthermore, ELVIS requires significantly less hardware capacity than previous approaches. The design is easily scaled; it requires hardware that grows linearly with formula size. As such, it is the first to guarantee polynomial space and time complexity of formula loading. This avoids the laborious (NP-hard) placement and routing of each formula that has plagued previous approaches. The new approach can efficiently support dynamic clause addition, formula partitioning, implication heuristics and an unbounded number of variables per clause. Large scale implementation of these optimizations and modifying ELVIS to realize a multi-chip board design are the goals of future research.

I/sub DDQ/ diagnosis is an important part of the Failure Analysis toy box, but it often requires substantial guesswork and intuition, especially when trying to divine the proper pass-fail threshold for the correct diagnostic result. This paper describes clustering and probability assignment algorithms designed to eliminate this guesswork by automatically determining diagnostic pass-fail thresholds, while using probabilistic techniques to allow for reasonable noise and error. We report the result of using these techniques on some of the failing chips from the Sematech experiment. The system describe first identifies appropriate thresholds and then pinpoints the correct diagnosis without requiring manual intervention and without requiring that the observed I/sub DDQ/ behavior perfectly matches the predicted I/sub DDQ/ behavior. The paper also discusses the use of information produced by inductive fault analysis and specialized fault simulation as part of the diagnosis process.

Diagnostic fault simulation can generate enormous amounts of data. The techniques used to manage this data can have significant effect on the outcome of the fault diagnosis procedure. We first demonstrate that if information is removed from a fault dictionary, its ability to diagnose unmodeled faults may be severely curtailed even if dictionary quality metrics remain unaffected; we, therefore, focus on methods for producing small, lossless dictionaries, We present a new dictionary organization based on error sets, which is amenable to standard data-compression techniques. We compare several dictionary organizations and the effect of standard data-compression techniques on each of them. An appropriate organization and encoding makes dictionary-based diagnosis practical for very large circuits.

Previously-proposed strategies for VLSI fault diagnosis have suffered from a variety of self-imposed limitations. Some techniques are limited to a specific fault model, and many will fail in the face of any unmodeled behavior or unexpected data. Others apply ad-hoc or arbitrary scoring mechanisms to fault candidates, making the results difficult to interpret or to compare with the results from other algorithms. This paper outlines an approach to fault diagnosis that is robust, comprehensive, extendable, and practical. By introducing a probabilistic framework for diagnostic prediction, it is designed to incorporate disparate diagnostic algorithms, different sets of data, and a mixture of fault models into a single diagnostic result. Results from diagnosis experiments on a Hewlett-Packard ASIC and FIB inserted defects are presented.

Automated fault diagnosis based on the stuck-at fault model is not always effective. This paper presents practical experiences in applying a bridging fault based diagnosis technique to a TI ASIC design. Results are presented for units into which known bridging defects have been introduced via a focused ion beam (FIB) machine.

This paper develops a Physical Design for Test (PDFT) metric that is directly related to the expected quality level (QL) contribution of a cell to a circuit, and it details experimental results showing the usefulness of this metric in predicting the quality level contribution of a cell to circuits that have yet to be designed. The PDFT metric shows what QL increase can be expected for the circuit by changing the physical design of a component of the circuit.

We describe a system for simulating and generating accurate tests for bridging faults in CMOS ICs. After introducing the Primitive Bridge Function, a characteristic function describing the behavior of a bridging fault, we present the Test Guarantee Theorem, which allows for accurate test generation for feedback bridging faults via topological analysis of the feedback-influenced region of the faulty circuit. We present a bridging fault simulation strategy superior to previously published strategies, describe the new test pattern generation system in detail, and report on the system's performance, which is comparable to that of a single stuck-at ATPG system. The paper reports fault coverage as well as defect coverage for the MCNC layouts of the ISCBS-85 benchmark circuits.

Successful failure analysis requires accurate fault diagnosis. This paper presents a method for diagnosing bridging faults that improves on previous methods. The new method uses single stuck-at fault signatures, produces accurate and precise diagnoses, and takes into account imperfect fault modeling; it accomplishes this by introducing the concepts of match restriction, match requirement, and match ranking.

Effective bridging fault diagnosis requires reducing the (/sub 2//sup n/) number of bridging faults to a handful of candidates. A preliminary step can reduce the O(n/sup 2/) candidates to a manageable O(n) candidates by using layout information to eliminate those bridging faults that are very unlikely to be shorted together. This step removes from consideration those faults that match the fault signature but are physically impossible. However, sometimes-perhaps due to issues of intellectual property or because the degree of information stored about a circuit changes over its lifecycle-the physical design of the circuit is not available, and the number of nodes is too large to explicitly consider all pairs. In this paper we present two ways to provide successful diagnoses without access to physical information. The second method produces optimal diagnoses under our ranking criteria. Either technique can be used in conjunction with information extracted from the physical design to allow for diagnoses of much larger circuits than previously possible.

Physical defects cause behaviors unmodeled by even the best fault simulators, which complicates predictive diagnosis. This paper reports on a diagnosis procedure that uses modified composite signatures constructed from single stuck-at information combined with a lexicographic matching and ranking algorithm. The diagnosis procedure is used to perform high-quality bridging fault diagnosis for more than 400,000 diagnostic experiments involving dropping or adding behaviors from the simulations of faulty circuits.

We define a network break as a break fault in the p-network or in the n-network of a CMOS cell that breaks one or more transistor paths between the cell output and V/sub dd/ or GND. Previous work, mostly in the context of transistor stuck-open faults, studied test invalidation due to transient paths to V/sub dd/ or GND, and due to charge sharing. In this paper we show the importance of Miller feedthrough and feedback capacitances in network break test invalidation, which was ignored by previous work. We present a new fault simulation algorithm for network breaks, with the following novelties: First, the electrical charge coming from Miller and p-n junction capacitances is computed using a transistor charge model; this automatically handles the nonlinear nature of transistor capacitances accurately, as opposed to assuming constant capacitance values as was done in previous work. Next, we use only six voltage levels for charge computations, which allows us to create look-up tables that dramatically reduce the computation time. Finally, the maximum voltage an internal node in an n-network can acquire is about three-fourths of the V/sub dd/ voltage (instead of V/sub dd/ as assumed by previous work), and similarly, a p-network node cannot discharge all the way down to the GND voltage. Using our simulator to analyze test sets for the ISCAS'85 circuits, we found that the charge coming from Miller capacitances has a larger share in test invalidation than the charge from p-n junction capacitances. Our simulator spends less time for charge computations than it spends for transient path identification.

We present a new fault simulation algorithm for realistic break faults in the p-networks and n-networks of static CMOS cells. We show that Miller effects can invalidate a test just as charge sharing can, and we present a new charge-based approach that efficiently and accurately predicts the worst case effects of Miller capacitances and charge sharing together. Results on running our fault simulator on ISCAS85 benchmark circuits are provided. 1 INTRODUCTION Defects that occur during the IC manufacturing process can be categorized into three classes according to Hawkins et al. [7]. These classes are bridge, open circuit, and parametric defects. Open circuit defects cause breaks in the conducting materials in the layout, and contacts are particularly susceptible to such breaks. Breaks can be divided into two categories: those that physically disconnect one or more transistor gates from their drivers, and those that disconnect transistors from each other in the p-network or n-network of ...

Precise failure analysis requires accurate fault diagnosis. A previously proposed method for diagnosing bridging faults using single stuck-at dictionaries was applied only to small circuits, produced large and imprecise diagnoses, and did not take into account the Byzantine Generals Problem for bridging faults. We analyze the original technique and improve it by introducing the concepts of match restriction, match requirement, and failure recovery. Our new technique, which requires no information other than that used by standard stuck-at methods, produces diagnoses that are an order of magnitude smaller than those produced by the original technique and produces many fewer misleading diagnoses than that of traditional stuck-at diagnosis.

It is assumed that tests generated using the single stuck-at fault model will implicitly detect the vast majority of fault-causing defects within logic elements. This may not be the case. In this paper we characterize the possible shorts in the combinational cells in a standard cell library. The characterization includes errors on the cell outputs, errors on the cell inputs, and excessive quiescent current. The characterization provides input vectors to stimulate these errors. After characterizing the faults that occur due to possible electrical shorts, we compare the coverage of the logic faults using a single stuck-at test set and tests developed specifically to detect these shorts. We discuss the effectiveness of I/sub DDQ/ testing for these faults.

Compares the accuracy, speed and applicability to test generation of existing bridge fault modeling solutions. The authors identify some previously undiscussed anomalous circuit behaviors, and describe the extent to which they affect bridge fault simulation and testing. Finally, they present a system for evaluating bridge fault models in a test generation environment, and present an experiment that provides an assessment of how defect coverage can be affected by a generating and checking model.>

Afier introducing the Primitive Bridge Function, a characteristic function describing the behavior of bridged components, we present a theorem for detecting feedback bridge faults.We discuss two diflerent methods of bridge fault simu- lation, one of which is new, and present experimental results relating the relative eficiency of the two njethods.We conclude that the new simulation method, Wire Memory bridge fault simulation, is more e#icient-especially for larger circuits.

Presents a sequential test generation method based on Boolean satisfiability. The method produces near-minimal test sizes. The authors discuss the flexibility provided by Boolean satisfiability to extend the fault model to realistic faults. Experimental results using ISCAS-89 benchmark circuits and comparisons with previously published results are presented.>

The author describes the Boolean satisfiability method for generating test patterns for single stuck-at faults in combinational circuits. This new method generates test patterns in two steps: first, it constructs a formula expressing the Boolean difference between the unfaulted and faulted circuits, and second, it applies a Boolean satisfiability algorithm to the resulting formula. This approach differs from previous methods now in use, which search the circuit structure directly instead of constructing a formula from it. The new method is general and effective. It allows for the addition of heuristics used by structural search methods, and it has produced excellent results on popular test pattern generation benchmarks.>

Many manufacturing defects in static CMOS circuits are not detected by tests generated using the traditional single stuck-at fault model. May of these defects may be detected as increased propagation time or as excessive quiescent power supply current (IDDQ). In this paper the authors consider the probable manufacturing defects and compare the costs of detecting them by the resulting excess IDDQ versus the cost of traditional testing methods.>

The authors compare the cost of testing for excess of I/sub DDQ/ caused by bridge, break, and transistor stuck-on faults versus the cost of traditional testing methods. It is shown that, since many defects, cause nonlogical faults, I/sub DDQ/ monitoring during the application of test vectors to an IC provides significantly higher defect coverage than using only conventional testing. The costs for I/sub DDQ/ testing are compared with those for SSF (single-stuck-at-fault) testing by modifying an existing SSF ATPG (automatic test pattern generation) system. It is concluded that test generation for I/sub DDQ/ faults is quicker and more complete than for equivalent SSF faults, and even without explicit I/sub DDQ/ test generation, I/sub DDQ/ monitoring can be added to existing SSF testing for increased defect coverage.>

A formal approach for the analysis of heuristics used in automatic test pattern generation for combinational circuits is presented. A test pattern generation system that constructs a satisfying assignment for a Boolean formula describing the legal set of tests is discussed. Heuristics as modifications to the formula or the satisfier acting on the formula are described. Experimental results are provided for the system as a whole, and for the effects of four heuristics.>

Most automatic test pattern generation systems for combinational circuits generate a test for a given fault by directly searching a data structure representing the circuit to be tested. The author describes a novel system that divides the problem into two parts: first it constructs a formula expressing the Boolean difference between the unfaulted and faulted circuits. Second, it applies a Boolean satisfiability algorithm to the resulting formula. The novel system can incorporate any of the heuristics used by structural search techniques. It is not only quite general but is able to test or improve untestable every fault in the popular Brglez-Fujiwara test benchmark (Int. Symp. Circuits and Systems, June 1985). Experimental results are presented.>