Demo Data from VLDB 2026 / reviewers in the wild / expert
Toshihiko Koju
dblp:36/3621
· DBLP profile ↗
5ranked-venue papers
4as first author
0since 2021 · last 2016
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 3 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 61% Electronic design automation · 30% Performance modeling and evaluation · 9% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › memory management › virtual memory
address translation |
0.2 | 1 | 2014 | Optimizing Memory Translation Emulation in Full System Emulators · ACM Trans. Archit. Code Optim. 2014 |
Electronic design automation › hardware verification and test › functional verification › emulation
full-system emulation |
0.2 | 1 | 2014 | Optimizing Memory Translation Emulation in Full System Emulators · ACM Trans. Archit. Code Optim. 2014 |
Memory systems › virtual memory management
software TLB |
0.2 | 1 | 2014 | Optimizing Memory Translation Emulation in Full System Emulators · ACM Trans. Archit. Code Optim. 2014 |
Performance modeling and evaluation
simulation |
0.1 | 1 | 2014 | Optimizing Memory Translation Emulation in Full System Emulators · ACM Trans. Archit. Code Optim. 2014 |
Methods — techniques the papers use, named apart from their topics
profiling · 0.2STLB optimization · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2016 | Re-constructing high-level information for language-specific binary re-optimizationabstractIn this paper, we show a binary optimizer can achieve competitive performance relative to a state-of-the-art source code compiler by re-constructing high-level information (HLI) from binaries. Recent advances in compiler technologies have resulted in a large performance gap between binaries compiled with old compilers and those compiled with latest ones. This motivated us to develop a binary optimizer for old binaries using a compiler engine for a latest source code compiler. However, a traditional approach to naively convert machine instructions into an intermediate representation (IR) of the compiler engine, does not allow us to take full advantage of optimization techniques available in the compiler. This is because the HLI, such as information about variables and their data types, is not available in such an IR. To address this issue, we have devised a technique to re-construct the HLI from binaries by using contextual information. This contextual information is a set of knowledge about specific compilation technologies, such as the conventions of data structures, the patterns of instruction sequences, and the semantics of runtime routines. With this technique, our binary optimizer has improved the performance of binaries generated from an older compiler by 40.1% on average in the CPU time for a set of benchmarks, which is close to the one due to a source-code recompilation with the same compiler engine, 55.2% on average. Toshihiko Koju, Reid Copeland, Motohiro Kawahito, Moriyoshi Ohara |
CGO | 1 |
| 2014 | Optimizing Memory Translation Emulation in Full System EmulatorsabstractThe emulation speed of a full system emulator (FSE) determines its usefulness. This work quantitatively measures where time is spent in QEMU [Bellard 2005], an industrial-strength FSE. The analysis finds that memory emulation is one of the most heavily exercised emulator components. For workloads studied, 38.1% of the emulation time is spent in memory emulation on average, even though QEMU implements a software translation lookaside buffer (STLB) to accelerate dynamic address translation. Despite the amount of time spent in memory emulation, there has been no study on how to further improve its speed. This work analyzes where time is spent in memory emulation and studies the performance impact of a number of STLB optimizations. Although there are several performance optimization techniques for hardware TLBs, this work finds that the trade-offs with an STLB are quite different compared to those with hardware TLBs. As a result, not all hardware TLB performance optimization techniques are applicable to STLBs and vice versa. The evaluated STLB optimizations target STLB lookups, as well as refills, and result in an average emulator performance improvement of 24.4% over the baseline. Xin Tong 0005, Toshihiko Koju, Motohiro Kawahito, Andreas Moshovos |
ACM Trans. Archit. Code Optim. | 2 |
| 2012 | Optimizing indirect branches in a system-level dynamic binary translatorabstractA dynamic binary translator (DBT) is a runtime system that translates binary code on the fly, for example to emulate the execution of the binary code on a processor with a different instruction set. One of the major sources of the overhead is the resolution of the branch target addresses for indirect branch instructions. Previous work has addressed this problem for a single virtual address space, but none has addressed it for multiple virtual address spaces in the context of the system-level DBT. This is challenging for compiler optimizations because the compiler cannot compute the virtual addresses of the branch targets for indirect branches at compile-time since they are affected by the runtime states of the emulated TLB. In this paper, we propose a new compiler optimization technique to address the problem for a system-level DBT. Our key idea is to use an offset from the virtual address of each page that contains a branch instruction, since this offset is not affected by the emulated TLB. We found that the compiler can often compute the offset using compile-time constants and that this approach significantly simplifies the guard code necessary for an indirect branch. We implemented this technique in a compiler of a system-level DBT for the z/Architecture. Our experimental results showed our technique can reduce the execution times of the CBW2 benchmarks, part of the standard LSPR benchmark, by up to 5.9% and 2.5% on average. Our analysis indicated that our technique was able to optimize 3.8% of the total dynamic instructions in the original binary code, while completely removing the guard code for 98.9% of these indirect branches. Toshihiko Koju, Ali Ijaz Sheikh, Moriyoshi Ohara, Toshio Nakatani |
SYSTOR | 1 |
| 2005 | An efficient and generic reversible debugger using the virtual machine based approachabstractThe reverse execution of programs is a function where pro-grams are executed backward in time. A reversible debugger is a debugger that provides such a functionality. In this pa-per, we propose a novel reversible debugger that enables reverse execution of programs written in the C language. Our approach takes the virtual machine based approach. In this approach, the target program is executed on a special virtual machine. Our contribution in this paper is two-fold. First, we propose an approach that can address problems of (1) compatibility and (2) efficiency that exist in previous works. By compatibility, we mean that previous debuggers are not generic, i.e., they support only a special language or special intermediate code. Second, our approach provides two execution modes: the native mode, where the debuggee is directly executed on a real CPU, and the virtual ma-chine mode, where the debuggee is executed on a virtual machine. Currently, our debugger provides four types of trade-off settings (designated by unit and optimization) to consider trade-offs between granularity, accuracy, overhead and memory requirement. The user can choose the appro-priate setting flexibly during debugging without finishing and restarting the debuggee. Toshihiko Koju, Shingo Takada 0001, Norihisa Doi |
VEE | 1 |
| 2003 | Regression Test Selection based on Intermediate Code for Virtual MachinesabstractRegression testing is testing applied to software that has been modified. It basically entails re-testing the software with previous test cases to confirm that the modifications made to the software do not have an adverse effect. But re-executing all test cases is normally cost prohibitive, and thus much research has been done on selecting test cases from a test suite without compromising the reliability of the software. These regression test selection techniques find test cases that will not detect any bugs in the modified software, and delete those from the next regression test suite. However, these techniques are based on analysis of source code. Recent programming environments have seen a proliferation of virtual machines. For example, programs written in Java and with the Microsoft .Net Framework are compiled into a platform-independent intermediate code which is executed. Such code could also be used for regression test selection. This especially holds for the Microsoft .Net Framework which handles various programming languages, such as Visual Basic and C++. Thus, this paper presents a safe regression test selection technique for virtual machine based programs. We especially target the Microsoft .Net Framework. Evaluation on 10 different examples resulted in an average of a 40.4% decrease in the cost of regression testing. Toshihiko Koju, Shingo Takada 0001, Norihisa Doi |
ICSM | 1 |