With shrinking technologies and increasing design complexities, it is common to have a large number of modes (functional, scan, test and so on) and corners (PVT device and interconnect). This leads to an explosion in the number of scenarios (#modes × #corners) that need to be validated for timing. While multiple tactics are required to handle this problem, one essential way to address this is by reducing the number of modes by merging individual modes into superset modes. However, with the overriding necessity to maintain sign-off accuracy, mode merging with high merge-factor is very complex. In this paper, we propose a novel automated timing graph based approach to mode merging that is designed to meet these requirements. By construction, there is an inbuilt validation that the merged constraints correctly model the intent of original constraints. This technology is tested on large industrial designs and the results are provided.

The automated generation of timing models from gate-level netlists facilitates IP reuse and dramatically improves chip-level STA runtime in a hierarchical design flow. In this paper we discuss two different approaches to model generation, the design flows they lend themselves to and results from the application of these model generation solutions to large customer designs.