An area efficient synthesis procedure targeting complete robust path delay fault testability (RPDFT) of scan-based circuits is described. It includes an efficient untestability identification algorithm for two-level and multilevel circuits. The implementation of the algorithm uses tautology checking instead of test pattern generation (TPG) resulting in a speed-up factor of 5 in comparison to today's fastest TPG methods. Exploiting that untestability identification capability, factorization is improved to first combining only those product terms in which the same literal is untestable and checking whether this eliminates the untestable fault. If not, cardinality matching is used to add the best-suited term that removes the untestable fault. Our method has been found to give better results in terms of RPDFT and area than reported before. In contrast to previously published papers, we found that technology mapping using tree covering does not always preserve RPDFT.

This paper presents RESIST, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scanbased circuits. Five test classes are introduced and their properties are discussed. We present an algorithm for deriving a logic system for TPG that results in an earlier recognition of conflicting value assignments. RESIST uses the logic system derived for each test class for an optimal search strategy. In contrast to other approaches, it exploits the fact that many paths in a circuit have common subpaths. RESIST sensitizes those subpaths only once, reducing the number of value assignments during path sensitization significantly. In addition, our procedure identifies large sets of untestable path delay faults without enumerating them. RESIST is capable of performing TPG for all path delay faults in all ISCAS-85 and ISCAS-89 circuits. For the first time, results for all path delay faults in circuit c6288 are presented. A comparison with other TPG systems revealed that RESIST is significantly faster than all previously published methods.>

An accelerated fault simulation approach for path delay faults is presented. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and nonrobust decision of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.>

The authors present DYNAMITE, a versatile and efficient automatic test pattern generation system for path delay fault. Based upon a ten-valued and a three-valued logic, the deterministic test pattern generation algorithm incorporated in DYNAMITE is capable of generating both robust and nonrobust tests for path delay faults. Particular emphasis has been placed on coping with the main disadvantage of the path delay fault model. The distinct features of DYNAMITE consist of the application of a powerful implication procedure and a stepwise path sensitization procedure, which has the capability of proving large numbers of path faults as redundant by a single test generation attempt. The delay test generation process is further optimized by the use of a new path selection procedure which aims at the identification of paths, which can successfully be sensitized, and the elimination of redundant, i.e., unsensitizable, paths.>

This paper presents an accelerated fault simulation approach for path delay faults. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and non-robust detection of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.