Evolvable hardware (EHW) addresses on-chip adaptation and self-configuration through evolutionary algorithms. Current programmable devices, in particular the analog ones, lack evolution-oriented characteristics. This paper proposes an evolution-oriented field programmable transistor array (FPTA), reconfigurable at transistor level. The FPTA allows evolutionary experiments with reconfiguration at various levels of granularity. Experiments in SPICE simulations and directly on a reconfigurable FPTA chip demonstrate how the evolutionary approach can be used to automatically synthesize a variety of analog and digital circuits.

A radial basis function neural network was successfully applied to an area which is relatively new for neural networks: a remote sensing application that provides estimates of water vapor content, an important parameter for climate modeling. The neural network provided results which are up to 32% better than had been previously obtained using conventional statistical methods on the same data. These results have implications for improved short-term weather forecasting and for long-term global climate modeling. The neural network approach is compared with the past and present operating algorithms at the National Oceanic and Atmospheric Administration. The radial basis function network's performance is compared with sigmoidal backpropagation network. Low-power electronic implementations of the neural methodology were explored to demonstrate the feasibility of placing the network on a remote sensing platform. This would permit processing the raw sensor data into information on the platform, eliminating the need to store the raw data, and helping to contain the expected explosion of climate data.

A novel analog focal-plane processor, the Vector Array Processor (VAP), is designed specifically for use in real-time/video-rate on-line lossy image compression. This custom CMOS processor is based architecturally on the Vector Quantization algorithm in image coding, The current implementation of the processor can handle codebook sizes of up to 128 vectors of dimensionality 16. The VAP performs vector matching in a fully parallel fashion, utilizing as its basic computational element the 'bump' circuit that computes the similarity between two input voltages and outputs a current proportional to this disparity.>

We report on a VLSI-based analog processor for fully parallel, associative, high-speed pattern matching. The processor consists of two main components: one, an analog memory matrix for storage of a library of patterns, and the other, a winner- take-all (WTA) circuit for selection of the stored pattern that best matches an input pattern. An inner product is generated between the input vector and each of the stored memories. The resulting values are applied in parallel to a WTA network for determination of the closest match. Patterns with up to 22% overlap are successfully classified with a WTA settling time of less than 10|is. Applications such as star pattern recognition and mineral classification with bounded overlap patterns have been successfully demonstrated. This architecture has a potential for an overall pattern matching speed in excess of 109 bits per second for a large (32-bit x 1000-pattern) memory.