Performance estimation is a crucial operation which drives the design space exploration in an application-specific instruction set processor synthesis. With the increase in the level of integration, the design space has considerably expanded, which makes the simulation-driven techniques inadequate due to their slow speed. Alternatively, there are approaches which estimate performance by scheduling the application on the available processor resources without generating code. These are much more effective in exploring a large design space. The technique reported in this paper presents a scheduler-based approach for register file-size exploration. The performance is estimated by computing the number of spills for a particular register file size. The concept of register reuse chains is used for local register allocation, while live variable analysis done across the blocks is used to estimate global register needs. The technique is fast, accurate, retargetable, and does not require code generation. We have generated and validated execution-time estimates for selected benchmarks for a RISC (ARM7TDMI) and a VLIW (TM-1000) processor. Further, we have shown that this approach is much faster than simulator-based techniques.

Performance estimation which drives the design space exploration is usually done by simulation. With increasing dimensions of the design space, simulator based approaches become too time consuming. In the domain of application specific instruction set processors (ASIP), this problem can be solved by scheduler based approaches, which are much faster. However, existing scheduler based approaches do not help in exploring storage organization. We present a scheduler based technique for exploring register file size, number of register windows and cache configurations in an integrated manner. Performances for different register file sizes are estimated by predicting the number of memory spills and its delay. The technique employed does not require explicit register assignment. The number of context switches leading to spills is estimated for evaluating the time penalty due to a limited number of register windows and cache simulator is used for estimating cache performance. The proposed technique has been validated for several benchmarks over a range of processors by comparing our estimates to the results obtained from standard simulation tools. The processors include ARM7TDMI, LEON and Trimedia (TM-1000).

Performance estimation is a crucial operation which drives the design space exploration in Application Speci c Instruction Set Processors (ASIP) synthesis. The usual approach to estimate performance is to do simulation. With increasing dimensions of the design space, simulator based approaches become too time consuming. This problem can be solved by scheduler based approaches, which are much faster. However existing scheduler based approaches do not help in exploring storage organization. This paper presents a scheduler based technique for exploring register le size in ASIP synthesis.

Interest in low-power embedded systems has increased considerably in the past few years. To produce low-power code and to allow an estimation of power consumption of software running on embedded systems, a power model was developed based on physical measurement using an evaluation board and integrated into a compiler and profiler. The compiler uses the power information to choose instruction sequences consuming less power, whereas the profiler gives information about the total power consumed during execution of the generated program. The used compiler is parameterized such that, e.g., the register file size may be changed. The resulting code is evaluated with respect to code size, performance, and power consumption for different register file sizes. The extracted information is especially useful during application analysis and architecture space exploration in application-specific integrated processor (ASIP) design. Our analysis gives the designer the ability to estimate the desirable register file size for an ASIP design. The size of the register file should be considered as a design parameter since it has a strong impact on the energy consumption of embedded systems.