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Greg Thorson

dblp:36/800 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
High-performance computing · 42% Interconnection networks and networks-on-chip · 16% Hardware accelerators and domain-specific architectures · 16%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing
collective communication
0.412020
An In-Network Architecture for Accelerating Shared-Memory Multiprocessor Collectives · ISCA 2020
High-performance computing › collective communication
collective communication optimization
0.412020
An In-Network Architecture for Accelerating Shared-Memory Multiprocessor Collectives · ISCA 2020
Interconnection networks and networks-on-chip
in-network computing
0.412020
An In-Network Architecture for Accelerating Shared-Memory Multiprocessor Collectives · ISCA 2020
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.412020
An In-Network Architecture for Accelerating Shared-Memory Multiprocessor Collectives · ISCA 2020
GPUs and heterogeneous computing
multi-GPU computing
0.412020
An In-Network Architecture for Accelerating Shared-Memory Multiprocessor Collectives · ISCA 2020
Memory systems
shared memory
0.112012
SGI® UV2: a fused computation and data analysis machine · SC 2012
High-performance computing
supercomputing
0.112012
SGI® UV2: a fused computation and data analysis machine · SC 2012
High-performance computing › collective communication
all-reduce
0.112020
An In-Network Architecture for Accelerating Shared-Memory Multiprocessor Collectives · ISCA 2020
Distributed systems › distributed machine learning
distributed training
0.112020
An In-Network Architecture for Accelerating Shared-Memory Multiprocessor Collectives · ISCA 2020

Methods — techniques the papers use, named apart from their topics

switch design · 0.4discrete-event simulation · 0.4UPC · 0.1SHMEM · 0.1OpenMP · 0.1NUMALink interconnect · 0.1MPI · 0.1
YearPublicationVenuePosition
2020 An In-Network Architecture for Accelerating Shared-Memory Multiprocessor Collectives
abstract
The slowdown of single-chip performance scaling combined with the growing demands of computing ever larger problems efficiently has led to a renewed interest in distributed architectures and specialized hardware. Dedicated accelerators for common or critical operations are becoming cost-effective additions to processors, peripherals, and networks. In this paper we focus on one such operation, the All-Reduce, which is both a common and critical feature of neural network training. All-Reduce is impossible to fully parallelize and difficult to amortize, so it benefits greatly from hardware acceleration. We are proposing an accelerator-centric, shared-memory network that improves All-Reduce performance through in-network reductions, as well as accelerating other collectives like Multicast. We propose switch designs to support in-network computation, including two reduction methods that offer trade-offs in implementation complexity and performance. Additionally, we propose network endpoint modifications to further improve collectives. We present simulation results for a 16 GPU system showing that our collective acceleration design improves the All-Reduce operation by up to 2x for large messages and up to 18x for small messages when compared with a state-of-the-art software algorithm, leading up to 1.4x faster DL training times for networks like Transformer. We demonstrate that this design is scalable to large systems and present results for up to 128 GPUs.
Benjamin Klenk, Nan Jiang 0009, Greg Thorson, Larry Dennison
ISCA3
2012 SGI® UV2: a fused computation and data analysis machine
abstract
UV2 is SGI's second generation data fusion system. UV2 was designed to meet the latest challenges facing users in computation and data analysis. Its unique ability to perform both functions on a single platform enables efficient, easy to manage workflows. This platform has a hybrid infrastructure, leveraging the latest Intel® EP processors providing industry leading computational power. Due to its high bandwidth, extremely low latency NUMALink®6 (NL6) interconnect, plus vectorized synchronization and data movement, UV2 provides industry leading data intensive capability. It supports a single operating system (OS) image up to 64TB and 4K threads. Multiple OS images can be deployed on a single NL6 fabric, which has a single flat address space up to 8PB and 256K threads. These capabilities allow for extreme performance on a broad range of programming models and languages including OpenMP[1], MPI, UPC[2], CAF[3] and SHMEM. The architecture, implementation and performance of UV2 are detailed.
Greg Thorson, Michael Woodacre
SC1