The integral nonlinearity (INL) of Digital-to-Time Converter (DTC) in fractional-N phase-locked loops introduces fractional spurs, especially at near-integer channels, resulting in increased jitter. To meet the strict jitter and spur performance requirements of high-performance wireless transceivers, minimizing the INL in DTC designs is crucial. This work presents a computer-aided, automated optimization methodology that focuses on addressing issues stemming from the uniform capacitor unit structure within the capacitor array in Variable-Slope DTC. These issues include parasitic resistance and capacitance, which distort the charging and discharging behavior of the capacitors, contributing to INL. By systematically optimizing the capacitor layout and mitigating parasitic effects, the methodology allows precise tuning of each capacitor unit in capacitor array to reduce INL, enhancing the overall performance of the DTC.

Integrated sensing and communication is a promising technology for enabling high-speed and low-latency commu-nication between connected vehicles. However, due to the unique characteristics of millimeter wave (mmWave) communication, such as severe path loss, susceptibility to blockage and beam alignment mismatch caused by positioning or sensing errors, outage probability analysis is critical to evaluate the performance of such systems. In this paper, we investigate the outage probability of mm Wave V2V communication systems in highway and urban scenarios with varying propagation environments and traffic densities. Furthermore, the optimal 3dB beamwidth is also derived for a given transmitting power and communication distance.

We propose a sensing-assisted dynamic beamforming method for robust vehicle-to-vehicle (V2V) communication between neighboring vehicles. For the proposed method, the main beam is directly steered towards the intended receivers and searching steps are not required. To maximize transmission throughput and avoid connection interruption caused by sensing uncertainties, higher directional gain for the interested field-of-view and lower sidelobe are expected. The problem is formulated as an array pattern synthesis problem that can be solved efficiently with the widely used semi-definite relaxation (SDR) methods.

A colocated multiple-input multiple-output (MIMO) radar system may be interested in sending different data stream to multiple communication sinks widely separated in different directions with a physical layer security feature, i.e., a time-division dual function radar communications (DFRC) mode. Conventional channel precoding methods do not depend on the contents of the data streams. In this paper, given communication channels, we directly optimize constant-modulus transmit waveforms for a colocated MIMO radar, such that those communication sinks can decode the data stream in their own manner. Given the constellations of communication sinks, we design codes for different transmit antennas. Different from the precoding method, we transmit the optimized codes instead of precoded codes into space if a code combination needs to be transmitted into space. Meanwhile, the code optimization method enables to distribute different powers into space and can avoid eavesdroppers in other spatial directions from decoding the information transmitted. Numerical results with phase shift keying (PSK) constellations indicate that this method can form several intended code constellations in different spatial directions and the accuracy is higher if more transmit antennas are available. Meanwhile, the eavesdroppers in other space directions have a messed code constellations and it is hard to decode useful information from received signal.

In this study, a constant false alarm rate (CFAR) decision scheme is devised for frequency diversity multiple‐input–multiple‐output (MIMO) radar. Under the assumption that there exists not only the unstructured disturbance but also the structured interference, a double threshold detector (DT‐MGLRT) based on the modified generalised likelihood ratio test (MGLRT) algorithm is proposed, of which the first stage deals with the unknown parameters and the second stage determines the final decision. It is proved that the proposed detector possesses a CFAR with respect not only to the unknown spectral properties of the unstructured disturbance but also to the structured interference distribution. Finally, some experiment results indicate that the proposed detection algorithm has 2 dB signal‐to‐interference‐plus‐noise power ratio improvement on average in detection performance at a low computation and communication cost over conventional detection algorithms.

An important step in multi-sensor data fusion is sensor registration, namely, to estimate sensors' range and azimuth biases from their asynchronous measurements. Assuming the target moves in a straight line with an unknown constant velocity, we propose a two-stage nonlinear least square (LS) approach to this problem. More specifically, in stage I, each sensor first estimates its own range bias individually, and then in stage II, all sensors jointly estimate their azimuth biases. We show that both of the nonconvex LS problems can be solved to global optimality under mild conditions. Simulation results show that the root mean square error (RMSE) of the proposed approach is quite close to the Cramér-Rao lower bound (CRLB) when the level of the measurement noise is small.

This paper presents a novel RFID tag chip with temperature sensor in 0.18μm standard CMOS process. It consists of four blocks: RF/analog front-end circuit, 192-bit non-volatile memory (NVM), temperature sensor and digital baseband circuit. A CMOS UHF rectifier with dynamic bias using switch capacitor is proposed to improve the efficiency of rectification, while avoiding using costly Schottky diodes. We design a 192-bit NVM in standard CMOS process based on FN tunneling phenomenon with extremely small current density. It dissipates only 1.8μW/3.6μW for reading/writing operation. A 0.8μW smart temperature sensor with ±1°C resolution without power hungry ADCs is achieved. As a result, the power consumption is 5.8μW, 6.8μW, and 8.6μW for reading sensor, reading NVM and writing NVM respectively. The chip core area is 0.6mm2in 0.18μm CMOS process.