Clustering single-bit flip-flops (SBFFs) into multi-bit flip-flops (MBFFs) effectively reduces power and area. However, excessive displacement during the clustering and legalization process may incur significant timing degradation. To address this issue, we propose the first comprehensive MBFF placement methodology that addresses excessive displacement caused by pre-placed cells during clustering and legalization while simultaneously optimizing timing, power, area, and bin utilization. Our methodology includes three main features: (1) a force model to relocate flip-flops and reduce timing violations, (2) a clustering and legalization process to reduce timing degradation caused by displacement, and (3) a multi-objective function to identify flip-flop candidates suitable for MBFF clustering. Our methodology outperforms all participating teams in the 2024 CAD Contest at ICCAD on Power and Timing Optimization Using Multi-Bit Flip-Flops, based on exactly the same settings.

The rapid advancement of CMOS technology has empowered modern integrated circuits (ICs) to handle increasingly complex tasks, which are crucial across various applications. However, achieving a balance between performance and energy consumption remains a challenge, particularly for edge devices such as cell phones and IoT sensors. Heterogeneous multicore systems, combining high-performance and energy-efficient cores, offer a promising solution for optimizing power while meeting performance requirements. Nevertheless, the continuous evolution of technology exacerbates reliability concerns in multicore systems, notably transient errors and aging effects. Previous studies have proposed various strategies, including task replication and Dynamic Voltage and Frequency Scaling (DVFS), to mitigate reliability degradation. However, the lack of holistic consideration for these mitigation techniques may inadvertently shorten the system's lifespan due to potential conflicts between them. Hence, this paper thoroughly analyzes the interplay between strategies for mitigating transient errors and aging effects. Subsequently, we introduce a novel reliability-aware task deployment framework aimed at significantly extending the system lifespan while adhering to a specified reliability target and minimizing overall energy consumption. Experimental findings demonstrate the efficacy of our framework, showcasing a 4.98x improvement in system lifespan and a 50% reduction in energy consumption compared to prior studies.

Heterogeneous multicore systems, which consist of high-performance and power-efficient cores, are emerging to satisfy the various demands on performance and power consumption. On the other hand, as CMOS technology continues to shrink in size, the aging effect, which can cause performance degradation or timing failures, has become a non-negligible threat to lifetime reliability. To overcome the challenges under the aging effect, various approaches have been proposed in previous studies. Most previous studies, however, did not consider the different characteristics of big and little cores. In addition, most of them do not consider critical tasks with the strict timing requirements present in real-time applications, resulting in early system failure. Therefore, considering different characteristics of cores and the presence of critical tasks, we propose an aging-aware task deployment framework for real-time systems. In this framework, for high-performance big cores, we propose a novel asymmetric aging-aware strategy. This strategy finds an energy-efficient task-to-core assignment to reserve some healthy cores at the early system life stage. The reserved cores are kept idle with the lowest voltage and can execute critical tasks at the late system life stage, extending the system lifetime. Meanwhile, the non-reserved cores use lower voltages to execute tasks, reducing the aging effect. For energy-efficient little cores, we adopt the symmetric aging-aware strategy to balance out the aging effect of each little core. With a balanced aging effect, the utilization of little cores is improved. In addition, we propose voltage/frequency boosting and task migration techniques to increase the number of cores that can meet the task timing constraints. Compared to the state of the art, the proposed framework can achieve 1.10x lifetime improvement and 5% energy reduction.