Edgard Cansio

dblp:362/0699 · DBLP profile ↗
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1ranked-venue papers
1as first author
1since 2021 · last 2025
0009-0005-1857-4074ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 50% Reconfigurable computing and FPGAs · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA implementation
0.912025
FPGA Implementation of a 1D-CNN Modulation Classifier for Radar Signals · FPGA 2025
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.912025
FPGA Implementation of a 1D-CNN Modulation Classifier for Radar Signals · FPGA 2025

Methods — techniques the papers use, named apart from their topics

VHDL · 0.91d convolutional neural network · 0.9
YearPublicationVenuePosition
2025 FPGA Implementation of a 1D-CNN Modulation Classifier for Radar Signals
abstract
In this paper, the VHDL implementation of a 1D convolutional neural network (CNN) intrapulse modulation classifier is discussed. The solution is designed for electronic warfare (EW) applications, whose main purpose is to detect and identify radar signals from potential threats in noisy environments, meeting stringent requirements related to classification accuracy and low latency. The presented classifier targets the Xilinx ZCU111 Development Board and is capable of identifying 14 modulation classes, as well as noise, under various signal-to-noise ratio (SNR) conditions. Results demonstrate that the field-programmable gate array (FPGA) implementation of the proposed classifier achieves an overall accuracy of 93% for signals with an SNR = -2 dB and at least 99% for SNR ≥ +10 dB, besides showing approximately 1.74× speed-up when compared to a processor-based approach of the same classifier.
Edgard Cansio
FPGA1