The demand for next-generation flexible electronics (FE) is rapidly increasing, especially in cost-sensitive consumer markets such as smart packaging, smart bandages, drug delivery systems, RFID tags, and wearable devices. Traditional silicon based electronics, constrained by high manufacturing costs and rigid form-factor, are inadequate for these emerging applications. However, the lack of rigid packaging in FE, combined with their complex and variable operating conditions, makes them more susceptible to thermal issues, therby leading to significant performance degradation, abnormal heating, and potential risks to device reliability and safety. To address these thermal challenges, we propose a novel approach to design thermal-resilient (TR) flexible analog neuromorphic circuits (f-NCs) based on amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). This cross-layer approach integrates TR circuit design for activation functions (AFs) and evolutionary algorithm (EA) based TR training using Neural Architecture Search (NAS) optimizing both the circuit-level thermal resilience and the architecture level training, ensuring robust performance of $\boldsymbol{f}$-NCs under varying thermal conditions. Experiments on 13 benchmark datasets demonstrate that thermal variations result in up to its $\mathbf{5 0. 3} \boldsymbol{\%}$ accuracy loss and the proposed evolutionary algorithm-based thermal-resilient training fully recovers this accuracy at the expense of $1.81 \times$ area and $1.39 \times$ power overhead.

Printed electronics (PE) enable lightweight, flexible, and low-cost devices for the Internet of Things (IoT) and wearable applications. Compared to conventional silicon-based electronics, PE trades peak performance for advantages in cost efficiency, mechanical flexibility, and large-area fabrication. However, its manufacturing processes remain unreliable and are prone to structural defects and variation due to inherent limited control in additive manufacturing. Printed neuromorphic circuits (pNCs) leverage the benefits of PE for on-demand analog edge computation in target applications but remain vulnerable to such defects. Diagnostic testing is therefore essential not only for detection but also for localizing faults to specific subcircuits and regions in the layout, a step critical for guiding yield improvement and reducing the cost of downstream inspection. We propose a diagnostic test pattern generation (DTPG) framework for fault localization in pNCs under black-box access. While ATPG is typically formulated as an optimization problem for fault detection, our approach extends this formulation by explicitly optimizing for fault distinguishability. On ten UCI datasets, the framework achieves up to 20.7% higher diagnostic coverage with a reduction of up to 3.6 times the number of undetectable subcircuits than detection-only test sets, while constraining the number of patterns to reduce storage overhead. These results demonstrate effective fault localization and establish a foundation for finer-grained, component-level diagnosis in future work.

Spin-Transfer Torque MRAM (STT-MRAM) is gaining popularity as a leading non-volatile memory (NVM) for embedded, IoT, and automotive systems, owing to its low leakage, high endurance, and compatibility with CMOS processes. However, its magnetic nature and non-volatility feature introduce unique fault behaviors that differ fundamentally from conventional volatile memories such as SRAM and DRAM. In particular, faults injected during MRAM write operations may persist across power cycles, enabling attackers to exploit stable key corruptions. In this work, we present a persistent fault analysis (PFA) framework targeting AES implementations where the round-key schedule is stored in STT-MRAM. We demonstrate how carefully timed voltage glitches during MRAM write cycles can create reproducible, persistent bit flips that propagate through the AES key schedule. These persistent corruptions significantly reduce the ciphertext requirements for differential fault analysis (DFA) and enable statistical persistent fault analysis (SPFA) with only 12–17 faulty ciphertexts. These findings highlight that MRAM-based systems are exposed to a persistent-fault threat model different from transient faults in volatile memories, with direct implications for secure key storage and cryptographic implementations.

With the rising demand for ultra-low-cost and flexible electronics in applications like smart packaging and wearable health monitoring, printed electronics provide an affordable, adaptable, and customizable alternative to conventional silicon. However, these systems often rely on printed batteries or energy harvesters with limited power capacity, making strict power budgets critical. Printed neuromorphic circuits (pNCs) are promising for their analog signal processing, reduced circuit complexity, and energy efficiency in low-power environments. Nonetheless, maintaining robust performance under strict power constraints remains challenging, necessitating advanced optimization techniques. In this work, we propose an augmented Lagrangian approach to enforce task-specific power constraints in pNCs, validated across 13 benchmark datasets. Our method preserves accuracy within strict power budgets while achieving Pareto-optimal power-accuracy trade-offs in a single training run. In contrast, the penalty-based method, which serves as the baseline, requires up to 150 runs per dataset to generate the Pareto front. For low-power scenarios ($\approx 20 \%$ of the original power), our method demonstrates a $52 \times$ improvement in accuracy-to-power ratio over the baseline. At higher power budgets $(\approx 80 \%$ of the original power), it achieves a $59 \times$ improvement, maintaining competitive performance. Experimental results demonstrate that our approach achieves $\mathbf{8 1. 8 2 \%}$ accuracy with p-tanh activation function (AF) at high power budgets and excels with p-Clipped_ReLU AF under low power constraints. This highlights the computational efficiency and effectiveness of our approach for power-constrained circuit design.

The rise of the Internet of Things demands flexible, biocompatible, and cost-effective devices. Printed electronics provide a solution through low-cost and on-demand additive manufacturing on flexible substrates, making them ideal for IoT applications. However, variations in additive manufacturing processes pose challenges for reliable circuit fabrication. Adapting neuromorphic computing to printed electronics could address these issues. Printed neuromorphic circuits offer robust computational capabilities for near-sensor processing in IoT. One limitation of existing printed neuromorphic circuits is their inability to process temporal sensory inputs. To address this, integrating temporal components in printed neuromorphic circuit architectures enables the effective processing of time-series sensory data. Printed neuromorphic circuits face challenges from manufacturing variations such as ink dispersion, sensor noise, and temporal fluctuations, especially when processing temporal data and using time-dependent components like capacitors. To mitigate these challenges, we propose robustness-aware temporal processing neuromorphic circuits with low-pass second-order learnable filters (SO-LF). This approach integrates variation awareness by considering the variation potential of component values during training and using data augmentation to enhance adaptability against physical and sensor data variations. Simulations on 15 benchmark time-series datasets show our circuit effectively handles noisy temporal information under 10% process variations, achieving an average accuracy and power improvement of ≈24.7% and ≈91% respectively compared to models lacking variation with ≈1.9×more devices.

Biologically-inspired Spiking Neural Networks (SNNs) have emerged as a promising avenue toward energy-efficient neuromorphic computing, particularly in edge applications such as soft robotics, wearable health monitors, and IoT devices. Printed Electronics (PE), offering advantages of ultra-low cost fabrication and mechanical flexibility, present a viable platform to realize such neuromorphic systems at scale. However, designing adaptable and efficient spiking circuits that meet the unique constraints of PE applications remains a challenge. To address this, we propose a novel analog spiking neuromorphic circuit with a learnable spike generator (LSG). Unlike fixed-threshold models, our generator adapts spike timing dynamics during training, enabling better task-specific performance. To optimize for ultra-low power consumption on resource-constrained platforms, we further introduce a robustness-aware training framework that further minimizes the energy consumption adaptively. Simulation results across 13 benchmarks demonstrate an average 57.6% power reduction for the LSG while improving the average classification accuracy by 8%, area and energy reduction by 89% and 28.7% respectively compared to the state-of-the-art printed analog spiking neural networks (P-SNNs).

The rapid advancement of flexible electronics (FE) has driven significant innovation across diverse sectors, including healthcare, wearables, smart packaging, and IoT devices, owing to their adaptability, lightweight form factor, and cost-effectiveness compared to traditional silicon-based electronics. A key computing paradigm in this domain is bespoke classifiers, where model parameters are hardcoded in neuromorphic hardware to meet strict area, power, and cost constraints. By tailoring bespoke hardware to specific tasks, these circuits achieve significant accuracy under tight resource budgets but also introduce distinct security vulnerabilities. The intrinsic flexibility of substrates, unconventional manufacturing processes, and limited protective packaging make such systems particularly vulnerable to security threats, with side-channel attacks (SCAs) being a critical concern. In this work, we systematically investigate SCA vulnerabilities in bespoke TFT-based multilayer perceptron (MLP) classifiers, considering both analog (flexible analog multilayer perceptron (f-AMLP)) and digital (flexible digital multilayer perceptron (f-DMLP)) realizations. For digital classifiers, we apply correlation power analysis (CPA), leveraging well-established leakage models from silicon-based systems. For analog classifiers, where leakage is continuous, nonlinear, and strongly influenced by device-level variability, we develop a tailored convolutional neural network (CNN)-based regression attack capable of extracting inputs from noisy power traces. Experimental results across benchmark datasets show that f-DMLPs can be compromised with 70–85% cumulative attack success rate (ASR) after ≈ 4k–5k traces using CPA, while f-AMLPs, though slower to attack initially, reach up to 90–95% ASR after ≈ 8k–9k traces with CNN-based approach.

Printed electronics (PE) is an emerging additive manufacturing technology, enabling flexible and extremely lowcost computing devices for future pervasive computing systems. Given the form factor and limited device count in this technology, Unary Encoding (UE), which encodes values as a sequence of bits (1’s or 0’s) by utilizing the proportion of 1’s in the sequence to represent the corresponding probability, shows great promise for printed technologies targeting resource-constrained applications. However, while UE offers some resilience to noise and variability, explicit error correction is still required to address intrinsic defects and variations in printing technologies to deliver reliable and stable outputs. In this work, we propose an area-efficient analog error correction (AEC) method using UE techniques to deal with sporadic bit errors and environmental noise at runtime. This approach significantly reduces transistor count and area utilization compared to conventional error correction coding (ECC) implementations. For proof of concept, we have shown the applicability of this approach for printed physical unclonable functions (p-PUFs) which have significantly lower reliability than silicon-based counterparts. Moreover, the robustness of the proposed scheme against temperature and voltage fluctuations has also been reported. By applying AEC to the p-PUFs output bitstream, its reliability can be fully restored (statistically 100%) for up to 20% bit error rate.

Printed electronics (PEs) is an additive fabrication technology which not only allows for a highly flexible printing of circuit patterns, but also produce soft, nontoxic, and degradable electronics at an extremely low cost. These properties make PE an enabler of new application domains, e.g., fast moving consumer goods and disposable healthcare devices. A particularly promising class of circuits in this technology is the printed analog neuromorphic circuits, offering efficient and highly tailored computational functionalities. In this work, we leverage the highly flexible fabrication process of PE to address the bottleneck of PE, i.e., the large feature sizes and low device counts. This issue is crucial, as it impairs the integration of printed circuits into target applications with limited footprint, such as smart band-aids. We propose an evolutionary algorithm (EA) to improve the circuit compactness through circuit architecture optimization. As baseline, we compare the proposed EA method with a state-of-the-art pruning method and a modified area-aware pruning method. All of them are able to optimize circuit architecture. Experimental simulation reveals that the proposed EA approach can effectively achieve compact circuits and outperform the pruning method by$3.1\times $lower area with no loss of accuracy. As a byproduct, the power is reduced by$3.0\times $, paving the way to energy-harvested printed systems.

The demand for next-generation flexible electronics in applications like smart packaging and smart bandages has driven the need for cost-effective solutions. Traditional silicon-based electronics struggle with high costs and rigidity, making them unsuitable for these emerging markets. In this regard, additive printed electronics (PE) offer a viable alternative with their flexibility and ultra-low-cost manufacturing. printed analog neuromorphic circuits (pNCs) are well-suited for these target applications, especially for classification tasks, as their low device count can efficiently meet the needs of the technology. However, low-cost additive manufacturing comes with higher defect rates, such as misprints, broken connections, and defective components, posing significant challenges to the reliability of printed circuits. This article presents a novel co-design of training algorithm and hardware for fault-tolerant pNCs using fault-aware training (FAT). The proposed method introduces a fault-tolerant version of printed nonlinear transformation circuits, combined with a bespoke training process that selects different types of printed activation functions (AFs) for different neurons to optimize both fault endurance and hardware costs. Experiments on benchmark datasets demonstrate an improvement in the accuracy of fault-tolerant (FT) pNCs from 62.1% to 79.4% under a 10% fault rate. Moreover, combining both normal and fault-tolerant versions of activation functions (AFs) using gumble-softmax distribution shows an acceptable accuracy drop with an average reduction in power and area of 54.5% and 6.54%, respectively, while reducing the training time significantly by 56.2%, compared to only using FT-AFs.

Computation-in-memory (CIM) is a promising solution to tackle the memory wall problem in big data and artificial intelligence applications. One possible approach to implement such a scheme is to use nonvolatile resistive memory technologies like spin transfer torque magnetic RAM (STT-MRAM) or resistive RAM (ReRAM). However, despite all the attractive features these technologies offer, they introduce new types of defects different from conventional SRAM technologies. Therefore, there is a need for dedicated testing algorithms that can detect such defects. In this paper, we proposed a testing scheme for CIM-capable memories that utilizes trim circuitry to dynamically switch between standard memory testing and CIM testing modes based on the speed and accuracy requirements, eliminating unnecessary testing overheads. This feature provides significant test time reduction while preserving the quality of the test. The proposed method is compatible with existing memory built-in self-test (MBIST) architecture and can be used for different types of emerging resistive memory technologies.

Printed electronics (PE) technology provides cost-effective hardware with unmet customization, due to their low non-recurring engineering and fabrication costs. PE exhibit features such as flexibility, stretchability, porosity, and conformality, which make them a prominent candidate for enabling ubiquitous computing. Still, the large feature sizes in PE limit the realization of complex printed circuits, such as machine learning classifiers, especially when processing sensor inputs is necessary, mainly due to the costly analog-to-digital converters (ADCs). To this end, we propose the design of fully customized ADCs and present, for the first time, a co-design framework for generating bespoke Decision Tree classifiers. Our comprehensive evaluation shows that our co-design enables self-powered operation of on-sensor printed classifiers in all benchmark cases.

Biologically-inspired Spiking Neural Networks have emerged as a promising avenue for energy-efficient, high-performance neuromorphic computing. With the demand for highly-customized and cost-effective solutions in emerging application domains like soft robotics, wearables, or IoT-devices, Printed Electronics has emerged as an alternative to traditional silicon technologies leveraging soft materials and flexible substrates. In this paper, we propose an energy-efficient analog printed spiking neuromorphic circuit and a corresponding learning algorithm. Simulations on 13 benchmark datasets show an average of 3.86 x power improvement with similar classification accuracy compared to previous works.

Printed Electronics (PE) is an emerging technology with flexible substrates and ultra-low-cost manufacturing, providing an appealing alternative to traditional wafer-scale silicon fabrication. With the increasing integration of various printed neural network (NN) architectures in diverse applications, the reliability of printed circuits has become a critical concern. This work provides a comprehensive analysis of the fault sensitivity on a variety of classification tasks for various digital and analog realizations of printed multilayer perceptrons (MLPs). We further evaluate different digital architectures, i.e., generic, bespoke, and approximate, to provide a comprehensive fault analysis on different benchmark datasets.

The market demand for next-generation flexible electronics is experiencing a significant upsurge, particularly in cost-sensitive consumer applications like smart packaging and smart bandages. These products are beyond the reach of traditional silicon-based electronics due to their high production cost and rigid form factor. Printed electronics (PE), with its adaptable and ultra-low-cost solutions, essentially meet the unique needs of these emerging application areas. This work presents a novel approach using an evolutionary algorithm (EA) to design highly bespoke printed analog neuromorphic circuits (pNCs) offering robustness against variability inherent in the printing process. By leveraging this algorithm and designing robust activation circuits, not only the resistances (weights) in the crossbar and parameters in the activation circuits, but also the types of nonlinear circuits (i.e., functional forms of activation functions) as well as the circuit topologies (neural architecture) can be learned to enhance the circuit robustness against printing variations. Experiments on 13 benchmark datasets demonstrate that, compared to the baseline, the proposed methodology can further outperform the normalized classification error rate by ≈ 55.38% and ≈ 25.11% under high-precision (±5%) and low-precision (±10%) printing scenarios, respectively. Moreover, the algorithm suggests the ReLU as the most robust activation function (AF) circuit family with only ≈ 21% susceptible to low precision (±10%) printing variation.

There is an increasing demand for next-generation flexible electronics in emerging low-cost applications such as smart packaging and smart bandages, where conventional silicon electronics cannot enter due to cost and form factor. In these domains, ultra-low-cost, high flexibility, and customizability are required. In this regard, printed electronics emerge as a complementary solution offering the aforementioned properties. To respect the constraints in those application scenarios and equip printed devices with the fundamental capability to process information, analog printed neuromorphic circuits offer multiple advantages, including strong expressiveness, streamlined circuit primitives, and a highly efficient machine learning-based design process. In this work, we focus on designing low-power printed neuromorphic circuits at the algorithmic level. By developing accurate power models for the circuit primitives, the power consumption can be considered into the design process. Subsequently, Pareto analysis is employed to examine the relationship between accuracy and power consumption. Experimental results reveal that, with the proposed approach, 2 x reduction of the power consumption can be realized while maintaining 95 % of classification accuracy. This approach has significant implications for the future development of energy-efficient printed neuromorphic circuits and their potential applications in IoT and AI intersections.