Database management systems (DBMSs) [1] provide a standardized interface for managing large amounts of data [2]. However, due to the volume of data DBMSs process, current processor-centric architectures (e.g., CPUs, GPUs, and FPGAs) suffer from data movement bottlenecks when executing key DBMS operations [3, 4]. Unlike processor-centric architectures, data-centric architectures, such as processing-in-memory (PIM) systems [4–55], can mitigate the main memory bottleneck in data analytics [4, 22, 33, 38, 56–61] by performing computation where the data resides, i.e., inside the main memory. Recently, industry has announced several PIM designs, including general-purpose PIM architectures, such as the UPMEM PIM system [44, 56, 62]. The UPMEM PIM system is implemented on standard DDR4-2400 DRAM technology. It consists of a set of PIM cores with private DRAM, called DPUs. An UPMEM PIM rank consists of 8 DRAM banks, which in turn consist of 8 PIM cores each. Each UPMEM PIM core has exclusive access to a $\mathbf{6 4 ~ M i B}$ DRAM (MRAM), 64 KiB scratchpad memory (WRAM), and $\mathbf{2 4} \mathbf{~ K i B}$ of instruction memory (IRAM).

Homomorphic encryption (HE) allows secure computation on encrypted data without revealing the original data, providing significant benefits for privacy-sensitive applications. Many cloud computing applications (e.g., DNA read mapping, biometric matching, web search) use exact string matching as a key operation. However, prior string matching algorithms that use homomorphic encryption are limited by high computational latency caused by the use of complex operations and data movement bottlenecks due to the large encrypted data size. In this work, we provide an efficient algorithm-hardware codesign to accelerate HE-based secure exact string matching. We propose CIPHERMATCH, which (i) reduces the increase in memory footprint after encryption using an optimized software-based data packing scheme, (ii) eliminates the use of costly homomorphic operations (e.g., multiplication and rotation), and (iii) reduces data movement by designing a new in-flash processing (IFP) architecture.

Large Language Models (LLMs) face an inherent challenge: their knowledge is confined to the data that they have been trained on.This limitation, combined with the significant cost of retraining renders them incapable of providing up-to-date responses.To overcome these issues, Retrieval-Augmented Generation (RAG) complements the static training-derived knowledge of LLMs with an external knowledge repository.RAG consists of three stages: (i) indexing, which creates a database that facilitates similarity search on text embeddings, (ii) retrieval, which, given a user query, searches and retrieves relevant data from the database and (iii) generation, which uses the user query and the retrieved data to generate a response.The retrieval stage of RAG in particular becomes a significant performance bottleneck in inference pipelines.In this stage, (i) a given user query is mapped to an embedding vector and (ii) an Approximate Nearest Neighbor Search (ANNS) algorithm searches for the most semantically similar embedding vectors in the database to identify relevant items.Due to the large database sizes, ANNS incurs significant data movement overheads between the host and the storage system.To alleviate these overheads, prior works propose In-Storage Processing (ISP) techniques that accelerate ANNS workloads by performing computations inside the storage system.However, existing works that leverage ISP for ANNS (i) employ algorithms that are not tailored to ISP systems, (ii) do not accelerate data retrieval operations for data selected by ANNS, and (iii) introduce significant hardware modifications to the storage system, limiting performance and hindering their adoption.