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Wangzhen Li

dblp:367/9185 · DBLP profile ↗
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3ranked-venue papers
1as first author
3since 2021 · last 2025
0009-0005-1005-0911ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 94% Performance modeling and evaluation · 6%
Theoretical computer science
1 paper
Algorithms and data structures · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › analog circuit design automation
analog circuit optimization
1.622025
MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing · DAC 2025
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Electronic design automation › circuit sizing
analog circuit sizing
0.912025
MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing · DAC 2025
Algorithms and data structures
algorithm portfolio
0.912025
MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing · DAC 2025
Electronic design automation
analog circuit synthesis
0.812024
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Performance modeling and evaluation
surrogate modeling
0.212024
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024

Methods — techniques the papers use, named apart from their topics

portfolio optimization · 1.7multitask gaussian process regression · 1.7asynchronous parallelization · 1.7subspace trust region · 0.8region acquisition function · 0.8gaussian process · 0.8batch bayesian optimization · 0.8
YearPublicationVenuePosition
2025 MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing
abstract
Numeric optimization methods are widely utilized to tackle complex analog circuit sizing problems, where the challenges include expensive simulations, non-linearity, and high parameter dimensionality. However, the diverse characteristics exhibited by different circuits result in varied optimization landscapes, making it difficult to identify a single algorithm that consistently outperforms others across all problems. In this paper, we introduce a multi-algorithm interworking optimization framework, which achieves optimization superadditivity based on a pool of member algorithms and a powerful algorithm-interworking protocol. We propose a computing resource reallocation method, which employs multitask Gaussian process regression and portfolio optimization techniques, leading to flexible and prudent online adaption of member algorithms. To efficiently utilize the computing resources for local exploitation, an evaluation data broadcast strategy enables cooperativeness across member algorithms. Besides, algorithms with different modeling overheads are integrated time-adaptively via an asynchronous parallelization mechanism. Comparative experiments against state-of-the-art algorithmcombining tools and optimization algorithms demonstrate the superiority of the proposed optimization framework.
Wangzhen Li, Ruiyu Lyu, Changhao Yan, Keren Zhu 0001, Zhaori Bi, Dian Zhou, Xuan Zeng 0001
DAC1
2024 AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis
abstract
Recent advances in machine learning (ML) for automating analog circuit synthesis have been significant, yet challenges remain. A critical gap is the lack of a standardized evaluation framework, compounded by various process design kits (PDKs), simulation tools, and a limited variety of circuit topologies. These factors hinder direct comparisons and the validation of algorithms. To address these shortcomings, we introduced AnalogGym, an open-source testing suite designed to provide fair and comprehensive evaluations. AnalogGym includes 30 circuit topologies in five categories: sensing front ends, voltage references, low dropout regulators, amplifiers, and phase-locked loops. It supports several technology nodes for academic and commercial applications and is compatible with commercial simulators such as Cadence Spectre, Synopsys HSPICE, and the open-source simulator Ngspice. AnalogGym standardizes the assessment of ML algorithms in analog circuit synthesis and promotes reproducibility with its open datasets and detailed benchmark specifications. AnalogGym's user-friendly design allows researchers to easily adapt it for robust, transparent comparisons of state-of-the-art methods, while also exposing them to real-world industrial design challenges, enhancing the practical relevance of their work. Additionally, we have conducted a comprehensive comparison study of various analog sizing methods on AnalogGym, highlighting the capabilities and advantages of different approaches. AnalogGym is available in the GitHub repository1. The documentations are also available at2.
Jintao Li 0002, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu 0001, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang 0001, Yun Li 0002, Xuan Zeng 0001
ICCAD4
2024 BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis
abstract
In this article, we propose a novel batch Bayesian and Gaussian process enhanced subspace derivative free optimization (DFO) method to solve high-dimensional and simulation-expensive analog circuit optimization problems. The existing optimization methods, such as Bayesian optimization and trust region-based DFO, suffer from under-fitting surrogate models in high-dimensional problems, which leads to inefficient optimization and suboptimal solutions. To address this issue, we propose a novel approach that integrates a batch Bayesian querying strategy for exploring the global design space and a Gaussian process (GP) enhanced subspace DFO method for exploiting promising regions in effective low-dimensional subspace. The GP is used to approximate the gradient pattern for subspace establishment, significantly enhancing the simulation efficiency. The selection of promising regions is based on an innovative region acquisition function that estimates the weighted local expected improvement. The effectiveness of the proposed method is demonstrated on real-life analog circuits, achieving${2.05\times - 17.65\times }$simulation number speedup and${1.37\times - 16.11\times }$runtime speedup compared with the state-of-the-art optimization methods.
Tianchen Gu, Wangzhen Li, Aidong Zhao, Zhaori Bi, Fan Yang 0001, Changhao Yan, Wenchuang Walter Hu, Dian Zhou, Xin Liu 0001, Zaikun Zhang, Xuan Zeng 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2