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Pouya Mahdi Gholami

dblp:368/7078 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2025
0009-0003-3051-1354ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Embedded and real-time systems · 100%
Artificial intelligence
1 paper
Efficient and distributed learning · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization
code generation
0.912025
Lupe: Integrating the Top-down Approach with DNN Execution on Ultra-Low-Power Devices · SenSys 2025
Embedded and real-time systems
intermittent computing
0.912025
Lupe: Integrating the Top-down Approach with DNN Execution on Ultra-Low-Power Devices · SenSys 2025
Machine learning › Efficient and distributed learning
on-device inference
0.312025
Lupe: Integrating the Top-down Approach with DNN Execution on Ultra-Low-Power Devices · SenSys 2025

Methods — techniques the papers use, named apart from their topics

top-down compilation · 2.6
YearPublicationVenuePosition
2025 Lupe: Integrating the Top-down Approach with DNN Execution on Ultra-Low-Power Devices
abstract
Executing deep neural networks (DNNs) on ultra-low-power (ULP) microcontrollers creates enormous opportunities for new intelligent edge applications. However, manually writing optimized DNN programs for ULP devices is time consuming and error prone due to the difficulty of managing on-device accelerators. Many prior works address this problem by creating special libraries that tailor common DNN building blocks for unique accelerators of ULP devices. This is a bottom-up approach, as developers build DNNs by assembling library calls. Unfortunately, the encapsulation overhead inherent in this approach greatly reduces accelerator utilization and overall performance. Instead, we advocate for a top-down approach. We present Lupe, a code generation framework, that converts high-level DNN algorithm descriptions to ULP-optimized code. Lupe provides top-down intermittent support that significantly reduces overhead while maintaining intermittent safety. We demonstrate Lupe's benefits on an MSP430 [54], achieving 12.36× and 2.22× average speedup over two prior works across a variety of DNN models in continuous power. Moreover, Lupe reduces the average intermittent runtime costs of prior works by 96.65% and 71.15%, respectively.
Mingyuan Xiang, Pouya Mahdi Gholami, Henry Hoffmann
SenSys2