This paper proposes a novel redundancy-based approach to drastically relax the matching requirements of CDACs and employing a cost-effective digital calibration method to improve linearity. The proposed architecture features a 3-segment CDAC with two redundant bits, which effectively reduces the overall DAC area and improves the DAC’s linearity. A 15-bit version of the DAC has been implemented in TSMC 0.18 μm technology, occupying a total area of 0.010 mm2. The design is validated through simulations in Cadence Spectre and calibration in MATLAB, resulting in worst-case integral nonlinearity (INL) and differential nonlinearity (DNL) of less than 0.5 LSB and 1 LSB, respectively, across 200 Monte-Carlo iterations.

High-resolution waveform generation is essential for Built-In Self-Test (BIST) and biomedical applications, where signal integrity is crucial. Traditional approaches rely on expensive Automated Test Equipment (ATE), highlighting the need for cost-effective alternatives. This paper presents a cheap approach for generating a 24-bit waveform using two low-cost 14-bit DACs enhanced with dithering to achieve high purity. A 14-bit ADC is employed as both the measurement device and, when needed, the Device Under Test (DUT) using the generated signal. Measurement results show that we achieve a signal with an Effective Number of Bits (ENOB) of 21 bits and distortions exceeding 130 dB, confirming the effectiveness of the design. The proposed approach provides a high-precision, cost-effective solution for embedded systems that require accurate signal generation, particularly for precision analog and mixed-signal (AMS) testing.

In this brief, we present the development of an on-chip sensor designed to monitor hot-carrier-induced (HCI) aging in NMOS transistors, utilizing the hot-carrier-induced series-resistance enhancement (HISREM) model. With a 10 MHz clock and SAR logic, the sensor generates a digital output proportional to device age under HCI stress, achieving 8-bit accuracy. Our methodology was developed using GF22FDSOI technology and evaluated over a 20-year period with extensive Cadence RelXpert simulations. We validate the sensors’ robustness to process variations and random mismatches through 200 Monte Carlo (MC) iterations. INL and DNL evaluation is used to ensure that the accuracy of the design is sufficient even in the worst-case corner conditions.

Testing high-resolution Digital-to-Analog Converters (DACs) often requires costly equipment, such as Automated Test Equipment (ATE) or high-resolution Analog-to-Digital Converters (ADCs). This paper presents a Built-In Self-Test (BIST) approach for high-resolution DACs, leveraging a 14-bit ADC to effectively test a 20-bit DAC. By embedding this solution within the DAC design, the proposed approach achieves scalability and significantly reduces test costs while maintaining good linearity and dynamic performance. The approach is validated through simulation results of the 20-bit DAC designed in GF22nm FDSOI technology and the BIST scheme modeled and validated using MATLAB. Results from 100 Monte Carlo simulations validate the robustness of the proposed testing scheme, achieving an INL estimation error of less than 0.4 LSBs.

Bias Temperature Instability(BTI) is an aging phenomenon in MOS transistors which is increasingly becoming one of the critical concerns for reliability of analog, digital and mixed-signal circuits, especially in deeply scaled technologies. This paper presents a robust integrated sensor that allows for the direct monitoring of the BTI-induced threshold voltage change of MOS transistors that have been subjected to stress. We achieve this by comparing a MOS transistor or device-under-test(DUT) which is stressed and is likely to suffer from BTI aging with a reference MOS device for which measures have been taken to ensure that it experiences negligible aging during its lifetime. The mixed-signal nature of the proposed sensor architecture allows for a direct physical-to-digital conversion of the BTI-induced threshold voltage change, as well as, fast measurements which is crucial because of the recovery effects of BTI. We also discuss a potential use case of proposed sensor for the online monitoring of an analog circuit.