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SangLyul Cho

dblp:369/3738 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2024
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1 · 1 since 2021Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
2 papers
Efficient and distributed learning · 50% Language models and text generation · 25% Deep learning architectures and training · 25%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Natural language and speech › Language models and text generation › large language model
large language model deployment
0.812024
Any-Precision LLM: Low-Cost Deployment of Multiple, Different-Sized LLMs · ICML 2024
Machine learning › Efficient and distributed learning
model compression
0.812024
Any-Precision LLM: Low-Cost Deployment of Multiple, Different-Sized LLMs · ICML 2024
Machine learning › Efficient and distributed learning › model compression
quantization
0.812024
Any-Precision LLM: Low-Cost Deployment of Multiple, Different-Sized LLMs · ICML 2024
Machine learning › Deep learning architectures and training
state space model
0.812024
VGA: Hardware Accelerator for Scalable Long Sequence Model Inference · MICRO 2024
Hardware accelerators and domain-specific architectures
FFT-based convolution
0.812024
VGA: Hardware Accelerator for Scalable Long Sequence Model Inference · MICRO 2024
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.812024
VGA: Hardware Accelerator for Scalable Long Sequence Model Inference · MICRO 2024

Methods — techniques the papers use, named apart from their topics

on-the-fly parameter generation · 1.5fast fourier transform · 1.5post-training quantization · 0.8
YearPublicationVenuePosition
2024 Any-Precision LLM: Low-Cost Deployment of Multiple, Different-Sized LLMs
abstract
Recently, considerable efforts have been directed towards compressing Large Language Models (LLMs), which showcase groundbreaking capabilities across diverse applications but entail significant deployment costs due to their large sizes. Meanwhile, much less attention has been given to mitigating the costs associated with deploying multiple LLMs of varying sizes despite its practical significance. Thus, this paper introduces any-precision LLM, extending the concept of any-precision DNN to LLMs. Addressing challenges in any-precision LLM, we propose a lightweight method for any-precision quantization of LLMs, leveraging a post-training quantization framework, and develop a specialized software engine for its efficient serving. As a result, our solution significantly reduces the high costs of deploying multiple, different-sized LLMs by overlaying LLMs quantized to varying bit-widths, such as 3, 4, ..., $n$ bits, into a memory footprint comparable to a single $n$-bit LLM. All the supported LLMs with varying bit-widths demonstrate state-of-the-art model quality and inference throughput, proving itself to be a compelling option for deployment of multiple, different-sized LLMs.
Yeonhong Park, Jake Hyun, SangLyul Cho, Bonggeun Sim, Jae W. Lee
ICML3
2024 VGA: Hardware Accelerator for Scalable Long Sequence Model Inference
abstract
Effectively modeling relationships between distant elements in a long input sequence is an important task that remains challenging to this day. The state-of-the-art models for processing sequential data are self-attention-based transformer models. However, the computational complexity of self-attention is quadratic to the input sequence length, which often becomes the limiting factor in scaling the sequence length. Recently, state space model (SSM)-based global convolution models, which replace attention with convolution, have been found to be effective for modeling long sequences, with a sub-quadratic complexity using Fast Fourier Transform (FFT). However, they show sub-optimal performance on data-parallel accelerators like GPU, due to the regions of extremely low compute utilization with memory bandwidth-bound operations. To address this inefficiency, this paper proposes the Vandermonde matrix Generating Accelerator (VGA), a custom accelerator that performs FFT-based convolution in an area/power-efficient manner. VGA introduces Complex number Compute Units (CCUs) to fully utilize the high on-chip SRAM bandwidth, and parameters are generated on the fly to drastically reduce the required SRAM capacity. VGA achieves 76×(48×) higher area (power) efficiency than NVIDIA A100 GPU when executing the global convolution operator of H3, a state-of-the-art SSM-based model.
Seung Yul Lee, Hyunseung Lee 0001, Jihoon Hong, SangLyul Cho, Jae W. Lee
MICRO4