For the state-of-the-art convolutional neural networks (CNNs), the accuracy of the inference is increased by raising the number of the layer. However, it can cause the higher computation complexities of the CNNs. The 3D CNN accelerator is applied to solve the computation complexities for the CNNs. However, the 3D CNN accelerator will encounter the serious thermal problem. In this article, we propose the predicted rate-controlled and task-allocated dynamic thermal management (prctaDTM) for the 3D CNN accelerator systems. The proposed prctaDTM contains the rate-controlled temperature prediction (RCTP), workload movement (WM), and workload adjustment (WA) to control the workloads of the 3D CNN accelerator and adjust the parallelism for the 3D CNN accelerator. The goal is to solve the thermal problem of the 3D CNN accelerator. In our experiments, the latency for the 3D CNN accelerator can be reduced by 18.1%–40.1% and the peak temperature for the 3D accelerator can be controlled close to the predefined thermal limitation. Moreover, the prediction errors with RCTP can be constrained below 0.66˚C for different CNN applications.

This paper presents an 8-bit asynchronous SAR ADC for CMOS image sensor applications in 130nm 1P4M technology. The proposed one-side merge-and-split switching effectively reduces the DAC switching energy because the reference voltage is halved. In addition, considering the bottom-plate parasitic capacitance, the proposed method can have better power efficiency compared to other methods. With 1.5V supply and Nyquist rate input, the prototype consumes 330μW at 16MS/s and achieves an ENOB of 7.21bit and a SFDR of 62.77dB, respectively. The resultant FoM is 139fJ/conv-step.

This paper presents a 10b 500KS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) with input range prediction DAC switching technique for low power applications. The proposed input range prediction DAC switching technique narrows down the traditional try-and-error range of the input signal to prevent unnecessary DAC switching, and the average switching energy is 90% more efficient than the conventional approach. A prototype is fabricated in 0.18um CMOS technology. With a single supply of 1V, it achieves an ENOB, SNDR and FoM of 9.24b, 57.3dB, and 47fJ/Conversion-step at 500KS/s sampling rate, respectively.