This session consists of three industry papers invited for their viewpoints on the challenges on future needs for low-power electronic design from an industry perspective. The authors are experts on the field of low-power design techniques as well as in CAD tools for implementing these techniques, both areas that are critical to actually achieving the goals of aggressive chip design. In addition, the authors provide a perspective of the lessons learned and the evolution of the techniques that have enabled mobile platforms to become so widely deployed and a big part of our everyday lives.

A RTL C-Based design and verification methodology is presented with enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor. The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow. It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development.

This paper discusses the problem of connectivity binding with geometric costs and a connectivity binder (GB) built to solve it. The goal of GB is to produce bindings with short interconnection lengths. This is important because routing can account for a significant portion of the layout area and long communication lines tend to lead to longer cycle times due to increased capacitance. Long lines also tend to increase power consumption, so it is important to decrease the interconnection lengths for low-power designs. This issue becomes even more critical as feature sizes are reduced. GB uses a new grid-based connectivity binding approach that incorporates these layout issues into the binding process. The usefulness of this grid-based approach is discussed and demonstrated.

The paper addresses the scheduling aspects of the problem of synthesizing control-dominated and processor-like systems from their behavioral descriptions. It is demonstrated that global mobility based scheduling can be used for fast design space exploration, generates schedules comparable to those produced by other global scheduling techniques, and can find operations to be moved into the branch delay slot created by a pipelined controller.>

A method is proposed for optimizing a Control I Data Flow Graph (CDFG), to generate shorter schedules, given a freed number of functional units.A counter-intuitive approach is taken of adding more operations to the CDFG to reduce the number of cycles in the final schedule.In this paper, this technique is applied to individual straight-line code sections (stateblocks) to reduce their execution times (as opposed to recently published methods for optim"zations that transcend state block boundaries).In many cases this technique has produced schedules significantly better (up to 30$%0) than those previously published.The algorithm rearranges the CDFG, modifjing the syntactical structure, while preserving the semantic meaning.The focus of attack is on the critical path, where most of the transformations are attempted to decrease the length of the critical path and hence the length of the resultant CDFG.The benchmarks were run on a MIPS RC3240 Riscomputer (-18 MIPS) and each schedule was derived at in less than 1 cpu second!

This paper addresses relevant issues in connectivity synthesis particularly with respect to other design concerns in high-level behavioral synthesis.A restricted model is used to run a series of design experimerus to provide insight into the relationship between scheduling, conrwctivity, and placement & routing.Contrary to the common approach of counting multiplexer, multiplexer inputs, and busses, this approach looks at more germanz issues, namely: I) How to decide how much a "bus" is really going to cost, 2) How much does "load balanced" scheduling help, especially in the case of resource constrained scheduling, and 3) Should the number of multiplexer inputs really be the main criterion for judging the connectivity quality of the designs?

The complexity of the assignment of operations to hardware components to specify the design at a register-transfer level, which is referred to as connectivity binding, is discussed. Connectivity binding is an important issue in high-level behavior synthesis systems that start with abstract behavioral descriptions and synthesize register-transfer level architectures for implementation. The corresponding decision problem is shown to be NP-complete and the complexity of the optimization problem is discussed. This research is intended to provide insight into the nature of this problem. It is shown that problems as simple as performing optimal function unit binding for a hardware structure containing only one commutative operator are hard.>

Outlines an integrated, multi-level VLSI synthesis system. First, an architectural synthesis tool is used to compile the high level behavioral specification of the target architecture into a register transfer level specification. Constraints are supplied as inputs to allow the user to selectively explore various portions of the design space. The goal is to let the user perform global design tradeoffs, while the system synthesizes the best designs that meet the user's constraints. Once the register transfer level description has been synthesized, the data path and control path are separated and control logic synthesis is performed. Boolean library descriptions of various components which have been presynthesized with a multi-level logic synthesis tool are used to construct the data path. Finally a gate matrix module generator is used to produce layout. With the availability of these low level synthesis tools, the high level architectural system need not rely on just estimates of delay, area, and power metrics for quantifying design alternatives.>

This paper describes behavioral compilation tools built for use in an intelligent silicon compiler. These tools allow the user or an expert system to compile behavioral descriptions to a register transfer level under user-imposed constraints. A flexible design model offers a combination of design features previously unavailable in behavioral compilers such as multicycle, chained, and pipelined function units along with the ability to choose between bus- and mux-based connectivity models. Furthermore, we present a new design strategy that allows easy exploratory design and we describe algorithms for state synthesis and connectivity binding that achieved higher quality designs than previous systems on selected benchmarks. The code for this project is run under 42 BSD Unix on a VAX 11 780 and is written in C.