Oftentimes, the power dissipation during the test mode far exceeds the power ratings of the normal operation mode. Hence, there is a need to reduce power during the test mode so that power ratings are not violated and chips do not get burnt during the application of test. Power consumption during built-in-self-test (BIST) operation can be minimized while achieving high fault coverage. Simple measures of observability and controllability of circuit nodes are proposed based on primary input signal probability (probability that a signal is logic ONE). Such measures help determine the testability of a circuit. We developed a tool, POWERTEST, which uses a genetic algorithm based search to determine optimal probability sets (signal probabilities or input signal distribution) at primary inputs to tradeoff test time versus power dissipation and fault coverage. The inputs conforming to the primary input probability-activity sets can be generated using cellular automata or linear feedback shift register (LFSR). We observed that a single input distribution (or weights) may not be sufficient for some random-pattern resistant circuits, while multiple distributions consume larger area. As a tradeoff, two distributions have been used in our analysis. Results on ISCAS benchmark circuits show that power reduction of up to 94.86% and energy reduction of up to 99.93% can be achieved (compared to equi-probable random-pattern testing) while achieving high fault coverage.