In industrial environments, publish/subscribe is essential for reliable and efficient machine-to-machine communication. Established protocols like Message Queuing Telemetry Transport (MQTT) and Advanced Message Queuing Protocol (AMQP), which implement this messaging pattern, have architectural limitations that hinder their ability to guarantee hard real-time requirements. To address this limitation, we propose combining MQTT for Sensor Networks (MQTT-SN), a lightweight UDP-based variant of MQTT, with Time-Sensitive Networking (TSN), a set of IEEE standards that enhance Ethernet with real-time capabilities. The resulting protocol, designated as MQTT-TSN, enables time-triggered publish/subscribe using the Time-Aware Shaper (TAS) and guarantees hard real-time compliance for MQTT-SN messages. In this work, we present a conceptual framework for the mapping of real-time MQTT-SN traffic to periodic time-triggered (TT) streams, incorporating configuration and adaptation at runtime. A case study demonstrates the feasibility and limitations of our approach in a simplified scenario.

The increasing demand for flexible, cost-effective sensor and control solutions in Industrial Internet of Things (IIoT) environments has led to a growing interest in using OPC UA on embedded microcontrollers. Although existing studies compare OPC UA to other IoT protocols, they often focus on larger boards or high-level development frameworks, leaving a performance gap for smaller devices with limited resources. In this paper, we benchmark version 1.4 of the open62541 OPC UA Client/Server stack on microcontroller-based systems (ESP32, STM32H747) as well as a more powerful edge platform (RevPi Connect 4). We measure round-trip times under varying client counts and polling rates, assessing near real-time capabilities comparable to traditional PLCs. Our results show that the ESP32 and STM32 can support moderate polling loads and a small number of parallel clients, with average latencies generally under 10 ms. For higher client loads and stricter real-time demands, the RevPi platform sustains sub-ms average latencies for up to 100 parallel clients. These findings inform hardware selection and guide industrial practitioners in deploying embedded OPC UA Client/Server solutions for simple sensor-monitoring tasks or more complex edge applications. We discuss implications and limitations of this approach. Finally, future directions in subscription-based communication and implementing standardized data models on resource-constrained devices are discussed.

The fast positioning of medical service robots in hospitals is a challenging task. Therefore, this paper presents a performance analysis around different LTE Positioning Protocol (LPP) transactions, which are performed over the user plane of a fifth generation (5G) network to transport position-related data. More precisely, the transaction time of the LPP capabilities and location information transactions is investigated depending on the number of additional technologies, such as Wi-Fi and Bluetooth, and the presence of a line of sight (LOS) connection to the serving 5G base station. For this purpose, a Lego Mindstorms EV3 robot, which is used with a Raspberry Pi Zero 2 W, a Quectel RM520N-GL 5G modem, an Archer T2U Nano Wi-Fi adapter and a BMP581 pressure sensor, is moving along three different real-world indoor scenarios: (i) The line of sight is always present, (ii) it is temporarily interrupted (N/LOS), and (iii) the line of sight is permanently broken (NLOS). The statistical results show that the number of used technologies influences the transaction time of LPP location information more than the corresponding LPP capabilities. If the Wi-Fi and Bluetooth technologies and a barometric pressure sensor are used together with 5G, the transaction time of LPP location information transfers increases by 2,521% (capabilities: 31.86%) in the LOS scenario compared to a 5G only case. In contrast, line of sight changes do not appear to have a clear negative impact on the transaction time of LPP capabilities and location information transfers, respectively.

Fast and accurate positioning of medical service robots is a challenging task. Therefore, this paper presents a performance analysis of various implementation designs around the Location Services User Plane Protocol (LCS-UPP), which is used in fifth generation (5 G) networks to transport positionrelated data. More precisely, the transport time of the LCSUPP is examined depending on the transported LTE Positioning Protocol (LPP) payload size, different Transport Layer Security (TLS) 1.3 implementations and the successive movement of the data path to the underlying Linux operating system. For this purpose, a Raspberry Pi Zero 2 W in combination with the Quectel RM520N-GL modem as a $\mathbf{5 G}$ user equipment (UE) as well as three additional Raspberry Pi 5 and the Ettus USRP B210 Software Defined Radio (SDR), which form the radio access and the core network, are used. The results show that the transport time of the LCS-UPP can be reduced by 42.01%, if the QUICbased MsQuic user space library is used instead of the wolfSSL library that based on the Transmission Control Protocol (TCP). Also the complete movement of the LCS-UPP data path to the Linux operating system decreases the transport time by 5.84% and 16.95% compared to the wolfSSL library and the in-kernel TLS implementation of Linux, respectively.

In Time-Sensitive Networking (TSN), Time-Aware Shaping facilitates the convergence of deterministic and lowpriority traffic in Ethernet networks. The allocation of bandwidth for low-priority traffic is crucial when scheduling timetriggered (TT) streams to prevent starvation and packet loss caused by queue congestion. This issue is particularly pertinent in online scheduling scenarios, where the deletion of streams can lead to schedule fragmentation. To prevent this issue, the time slots of the TT streams must be compressed to provide larger contiguous gaps for low-priority traffic in the schedule. In this paper, we present a novel heuristic approach for compressing schedules, which facilitates the grouping of time slots into units, thereby increasing the bandwidth for low-priority traffic and improving the schedulability of future streams. The proposed heuristic can be tailored to specific use cases through adaptive weighting, allowing a comprehensive evaluation of time slots according to the properties of the associated time slot units, TT streams, and the network.

The proliferation of wireless mobile devices has led to a growing interest in indoor localization applications, such as context-aware services in healthcare. However, the inherent complexities of multipath and non-line-of-sight (NLoS) in indoor environments pose significant challenges to conventional localization methods, often resulting in compromised accuracy. In this paper, we propose a localization approach for wireless systems that uses self-supervised learning and dissimilarity metrics derived from Received Signal Strength Indicator (RSSI) and Angle-of-Arrival (AoA) data to increase the accuracy of indoor localization in NLoS environments. Recent developments showed that self-supervised machine learning with channel state information (CSI) can accurately estimate positions without ground truth data. Accessing the CSI data can be challenging, so we present an approach that uses the more accessible RSSI values and AoA angles. Our evaluation of various neural network architectures and training parameters indicates that employing dissimilarity metrics derived from AoA and RSSI with selfsupervised learning is a promising approach.

The development of modern heterogeneous systems requires early integration of the various domains to improve and verify the design. Heterogeneous virtual prototypes are a key enabler to reach this goal. In order to efficiently support the development, their high simulation speed is of utmost importance. This article introduces measures to speed-up SystemC analog/mixed-signal (AMS) simulations which are commonly used to simulate the AMS part jointly with the digital prototype in SystemC. Two approaches to integrate variable-step ordinary differential equation solvers into the simulation semantics of SystemC AMS are presented. Both of them avoid global backtracking. One is well suited for feedback loops and the other is favorable for systems dynamically reacting onto events. Moreover, a timestep quantization is developed that overcomes the recurrent matrix inversion bottleneck of variable-step implicit solvers. A similar method is then used to increase the simulation speed of electrical linear network models with high switching activity. Various experiments from the context of smart sensors are presented which prove the effectiveness for enhancing the simulation speed.

The analog/mixed signal extensions to SystemC effectively tackle the needs for heterogeneous system integration using virtual prototyping. However, they introduce the inherent trade-off between accuracy and performance due to the discrete timestep. Besides the discrete-time scheduler, analog solvers are used within SystemC-AMS to solve linear ordinary differential equations (ODEs). In this paper, we derive two methodologies to integrate adaptive ODE solvers into SystemC-AMS that estimate the optimal timestep based on error control. The main advantage of the approaches is the avoidance of time-consuming global backtracking. Instead, they fit well into the execution semantics and scheduling approach of SystemC-AMS. A detailed comparison of both integration schemes is given and they are evaluated using a MEMS accelerometer as classical example of a heterogeneous system.

WLAN Mesh Networks (WMNs) are a promising network architecture for IoT applications due to their self-healing and robust network formation capabilities. The IEEE 802.11s amendment standard integrates mesh functionality into the WLAN MAC layer, ensuring seamless peering and routing. Initially designed for testing, the Linux implementation of IEEE 802.11s includes basic peer link blocking mechanisms. Based on this, we present a new MAC address filtering approach for reliable topology control in WLAN mesh networks. Our modifications to the Linux kernel enable persistent link blocking and bidirectional link teardown, preventing the sporadic establishment of unwanted connections. Real-world experiments demonstrate the effectiveness of our approach.

In this paper, we present the integration of MQTT for Sensor Networks (MQTT-SN) into OPC Unified Architecture (OPC UA) as a novel publish/subscribe (PubSub) protocol binding in order to enhance the industrial communication stack. By leveraging the lightweight MQTT-SN protocol, which is currently not considered in the architecture, we improve OPC UA's capability for high-frequency, low-latency messaging, which is essential for Industrial Internet of Things (IIoT) applications. We discuss related work and describe the design and implementation in detail. Our hybrid approach combines the rich data modeling and security capabilities of OPC UA with the communication efficiency of MQTT-SN, providing a scalable solution for real- time data management in industrial automation systems.

We present BurstLR, a novel online resynchronization method for wireless burst transmitted sensor signals. Instead of clock alignment, our method uses approximative timestamp realignment by estimating the relation between sensor clock and receiver clock at the receiver. Only the sensor and arrival timestamps of samples are required. Thus, no additional communication as well as hardware is needed. In our experiments with two wireless sensor nodes (Nicla Sense ME), we achieved a reduction of the average quadratic distance with dynamic time warping between resynchronized acceleration signals that recorded the same arbitrary human motion trajectory by 54.95 % to 76.91 % compared to signals that used the arrival times for synchronization.

Real-time capability plays an important role in modern factory communication systems. However, protocols such as MQTT, CoAP, and MQTT-SN, which are increasingly finding their way into industrial environments alongside industrial-grade protocols such as OPC UA and DDS, cannot fulfill the timing requirements without further optimization. In this paper, we present extensions of MQTT-SN to improve the real-time behavior in combination with PREEMPT_RT, which provides different real-time mechanisms for the Linux kernel. We address general, operating system-based, and hardware-specific optimizations. Their benefits are demonstrated by measurements in a practical testbed. The proposed extensions reduce delay and jitter, but do not aim to guarantee an upper bound on end-to-end delay.

In this study, the authors examine the technical challenges associated with wireless localization algorithms in indoor environments. The paper presents an in-depth analysis of various wireless communication technologies, meticulously summarizing their salient features and their implications within the broader scope of research. The outcomes of this study contribute significant technical insights into the capabilities and limitations of Joint Communications and Sensing (JCAS) technology. These insights are pivotal for advancing seamless data exchange and achieving comprehensive connectivity in the realm of 6G wireless communication networks, particularly those that integrate localization functionalities. The detailed findings of this research are poised to inform and influence subsequent technical research and developmental strategies in this specialized field.

We present a flow to reuse system-level analog/mixed-signal (AMS) models developed in MATLAB/Simulink for the extension of virtual prototypes in SystemC. To prevent time-consuming co-simulation, our flow translates the Simulink model into an equivalent SystemC-AMS model. Translation is supported either by wrapping code generated by MATLAB's Embedded Coder or by instantiating previously generated models. Thus, a one-to-one mapping of the model's hierarchy is possible which allows deep insights into the architecture and good traceability. The conducted case study on an accelerometer model shows the applicability of our approach. The generated hierarchical model is half as fast as a monolithic version but allows better observability and traceability of the system. It is tens of times faster than simulation in Simulink. The extended virtual prototype aims to support software engineers during development and validation of firmware in smart sensors.

The growing number of ultra-low power sensor applications drives the processing requirements "on-the-edge" and increases the demand for smart sensors, which implement signal processing and algorithmic features in firmware. Virtual prototyping in SystemC has become a major field of interest to validate the firmware and allow a seamless integration. However, the capability of SystemC is limited to discrete-time applications and cannot handle the full sensor system including its analog front end and mechanical part. Consequently, the firmware validation is often limited to oversimplified scenarios. In this paper, we present a virtual system prototype (VSP) using SystemC and its analog/mixed-signal (AMS) extensions which permits the validation of complex firmware features with tight interaction to the sensor element. The key benefit of this approach is an improved controllability and observability during the sensor firmware development even in early design phases. An industrial case study of a MEMS accelerometer and gyroscope is used throughout the paper to illustrate the proposed approach. A performance analysis proves the pracitcal relevance of our full-stack VSP as the simulation time is increased by a factor less than five compared to a pure SystemC approach without any functionality in the analog or physical domain.

The growing capabilities of wireless communication technologies such as WLAN-based systems enable their successful adoption in an ever-increasing range of applications. Particularly in the domain of the internet of things, the trend towards wireless interconnection is driven by its improved scalability and flexible, low-cost deployment compared to wired systems such as Ethernet. To handle the growing complexity of their design, developers need a process for early performance evaluation of these communication-intensive networked embedded systems. For this, established network simulation frameworks like ns-3 and ${OMNeT}++$ are often utilized. These frameworks require developers to model every part of their system, including the protocol stack and the target application they are developing. From the developers’ perspective, a workflow that would enable them to use real target software as much as possible is desirable. The available solutions to couple real target software with a network simulation, however, often exhibit several limitations. These range from a lacking detail level of the channel simulation to the requirement of access to the source code of every part of the system under design, and often prevent adoption of these coupling solutions. In this paper, we propose a data interface for the established simulator ns-3 that allows coupling to the Linux kernel at a very low level of the protocol stack, namely the lower WLAN MAC layer. This interface allows the performance evaluation of WLAN-based systems, in which real target code of almost the entire software stack can be used. With such an interface, developers can write real target software and test it under different wireless network scenarios and channel conditions, powered by a simulation using ns-3. We show the practicality of our interface by comparing it to a simulation solely performed in ns-3, as well as to another framework for coupling real target software to a channel simulation.

Due to the increasing complexity of distributed embedded systems, the development process demands early substantiation of design decisions for the targeted system. Virtual prototypes enable an early validation of hardware/software systems and they have proven to be very beneficial for target software development. However, these prototypes often do not include models for inter-device communication aspects of distributed systems. Especially the use of wireless communication has a significant impact on the overall system behavior and performance. This paper introduces a SystemC model of an essential part of IEEE 802.11 Wireless LAN communication, the Enhanced Distributed Channel Access (EDCA) protocol. In comparison to widely used network simulations, the modeling with SystemC promises an easier integration into existing virtual prototypes. EDCA is the main part of the lower medium access layer (MAC) of IEEE 802.11 and interfaces to the physical-layer communication as well as to non-time-critical higher MAC-layer functions. We conducted experiments with an additional simple physical communication channel model to compare our solution in terms of precision and performance to the well-established network simulator ns-3. We show that our model differs by $\approx 0.3 \%$ of retransmitted frames and an accompanied difference of the overall simulated transmission time of $\approx 0.45 \%$. It meets the overall expectations for the stochastic EDCA protocol. Moreover, the presented model has a significantly better simulation performance with $3 \cdot 10^{-5}$ s wall-clock time per frame, which is at least two orders of magnitude better than with the compared ns-3 simulation.

Sensor subsystems are becoming more complex as they increasingly take on various tasks, from signal processing to pattern recognition. This off-loading of continuous processes can decrease power consumption of the entire system, as the application processor of e.g. a smartwatch can spend more time in low-power modes. The design and validation of these sensor subsystems are thus becoming more difficult and time-consuming. This development process relies heavily on the availability of suitable sensor signals for testing. We propose a modular component-based framework to generate a multitude of tests using either prerecorded sensor signals or artificial signals to allow for a faster and more thorough development process and prototyping.Using the recently proposed Sensor-in-the-Loop architecture, the work at hand demonstrates not only the ability to test and develop the software offline in a simulation, but to also use the augmented sensor signal data directly on the hardware prototype at run-time. The framework can be used in various testing- and development setups to simulate sensor characteristics, processing steps and errors. We show, based on three comprehensive examples, that the proposed framework is able to simulate the common errors found in inertial MEMS sensors, generate signal traces to develop, train, and evaluate gesture recognition algorithms, and simulate pre-processing steps in order to evaluate their feasibility before they are implemented in the sensor firmware.

Smart inertial sensors have emerged in the last years enabling developers to implement sensor fusion or tasks like gesture detection directly in the sensor hardware and thus reducing the processing latency and energy consumption. The development of software for smart inertial sensors however faces difficulties from the limited hardware capabilities of the μC hardware and the lack of options to conduct reproducible tests directly on the hardware. We propose a Sensor-in-the-Loop architecture that allows a developer to record data from a smart sensor and inject the recorded data back into the sensor at a later time to evaluate the performance of the software in a reproducible way. With the proposed architecture it is possible to examine the performance and computational load on real hardware with recorded data thus allowing developers to optimize and improve the software in a more targeted way. In our implementation, the memory overhead for the code instrumentalization is just 0.63 %. The used RTT interface is at least four times faster than the regular SPI sensor interface. In experiments, we show that our proposed architecture is able to record and inject data of up to three 3-DOF sensors with 1.6kHz sampling frequency in real time.

Recently, it has been shown that constraint-based symbolic solving techniques offer an efficient way for deciding binding and routing options in order to obtain a feasible system level implementation. In combination with various background theories, a feasibility analysis of the resulting system may already be performed on partial solutions. That is, infeasible subsets of mapping and routing options can be pruned early in the decision process, which fastens the solving accordingly. However, allowing a proper design space exploration including multi-objective optimization also requires an efficient structure for storing and managing non-dominated solutions. In this work, we propose and study the usage of the Quad-Tree data structure in the context of partial assignment evaluation during system synthesis. Out experiments show that unnecessary dominance checks can be avoided, which indicates a preference of Quad-Trees over a commonly used list-based implementation for large combinatorial optimization problems.

An efficient Design Space Exploration (DSE) is imperative for the design of modern, highly complex embedded systems in order to steer the development towards optimal design points. The early evaluation of design decisions at system-level abstraction layer helps to find promising regions for subsequent development steps in lower abstraction levels by diminishing the complexity of the search problem. In recent works, symbolic techniques, especially Answer Set Programming (ASP) modulo Theories (ASPmT), have been shown to find feasible solutions of highly complex system-level synthesis problems with non-linear constraints very efficiently. In this paper, we present a novel approach to a holistic system-level DSE based on ASPmT. To this end, we include additional background theories that concurrently guarantee compliance with hard constraints and perform the simultaneous optimization of several design objectives. We implement and compare our approach with a state-of-the-art preference handling framework for ASP. Experimental results indicate that our proposed method produces better solutions with respect to both diversity and convergence to the true Pareto front.

WLAN mesh networks are one of the key technologies for upcoming smart city applications and characterized by a flexible and low-cost deployment. The amendment IEEE 802.11s introduces low-level mesh interoperability at the WLAN MAC layer. On the physical layer, IEEE 802.11n introduced major improvements such as HT data rates, MIMO techniques, and frame aggregation. However, building large-scale 802.11n/s testbeds and reproducible setups is challenging and costly. On the other hand, existing attempts for down-scaling real-world setups are limited to works without support for 802.11n and 802.11s. We therefore present Mini-Mesh, a miniaturized indoor 802.11n/s testbed. Following a transmission range scaling approach, we deploy a 6×6-node mesh grid on an area of only 1 m2. We validate the applicability of our method via comparative measurements, exhibiting a deviation of less than 6 % between a scaled indoor and unscaled outdoor setup. Based on these results, we parameterize a path loss model helping us to estimate outdoor dimensions for arbitrary indoor mesh topologies.

The design of embedded systems is becoming continuously more complex such that efficient system-level design methods are becoming crucial. Recently, combined Answer Set Programming (ASP) and Quantifier Free Integer Difference Logic (QF-IDL) solving has been shown to be a promising approach in system synthesis. However, this approach still has several restrictions limiting its applicability. In the paper at hand, we propose a novel ASP modulo Theories (ASPmT) system synthesis approach, which (i) supports more sophisticated system models, (ii) tightly integrates the QF-IDL solving into the ASP solving, and (iii) makes use of partial assignment checking. As a result, more realistic systems are considered and an early exclusion of infeasible solutions improves the entire system synthesis.

In sensor-based activity recognition often huge amounts of data have to be acquired from multiple sensors, which need to be communicated for further processing. When using wireless sensor nodes, energy efficiency is of outstanding importance, since it directly influences the time until the battery needs to be recharged. However, communicating a huge amount of sensor data over wireless interfaces causes high energy consumption as well. Furthermore, the host controller receiving the sensor data is hindered of using its low power modes, as it needs to be woken up more frequently as well. In the paper at hand, we introduce our approach of reducing energy consumption of sensor nodes in online activity recognition scenarios by calculating the feature extraction on the sensor subsystem itself. By doing so, we can reduce the output rate of the sensor which enables the host controller to stay in its low power modes for longer periods. Additionally, this approach drastically reduces the amount of data to be transmitted over wireless interfaces, which further improves energy consumption. In our experiments, the proposed approach reduces the energy consumption of a sensor node by up to 33 %.

WLAN mesh networks are characterized by their flexible and low-cost deployment, scalability, and self-healing capabilities. The new WLAN standard IEEE 802.11s introduces low-level mesh interoperability. However, building large-scale real-world test beds and reproducible setups is challenging and costly. In the majority of research works, network simulation is preferred over practical measurements. Here, the main disadvantage exists in simplified device and protocol models restricting the comparability to practical implementations. In contrast, using device emulation still requires the simulation of wireless channel and environment models. Consequently, a combination of both emulation and simulation is needed to enable virtual prototyping of real applications and protocols in WLAN mesh networks. Nevertheless, the computation of complex wireless channel effects requires a decoupling of wall clock and simulation time. Therefore, we present ViPMesh, a virtual prototyping framework for IEEE 802.11s and its Linux reference implementation. ViPMesh relies on WLAN device emulation and nested virtualization using QEMU and Linux containers to support the analysis of real applications on top of an unmodified protocol stack. Adopting an alternative time source approach for QEMU, ViPMesh acts as discrete-event simulator. It further integrates channel and environment models with support for IEEE 802.11n MIMO techniques, high throughput modes, multi-channel operation, and node mobility. To the best of our knowledge, this is the first approach that combines the IEEE 802.11s reference implementation with the described simulation features. The functionality of ViPMesh is demonstrated in different example scenarios.

Application modeling using dynamic dataflow graphs is well-suited for multi-core platforms. However, there is often a mismatch between the fine granularity of the application and the platform. Tailoring this granularity to the platform promises performance gains by (a) reducing dynamic scheduling overhead and (b) exploiting compiler optimizations. In this paper, we propose a throughput-optimizing compilation approach that uses Quasi-Static Schedules (QSSs) to combine actors of static dataflow subgraphs. Our proposed approach combines core allocation, QSSs, and actor binding in a Design Space Exploration (DSE), optimizing the throughput for a number of available cores. During the DSE, each implementation candidate is compiled to and evaluated on the target hardware---here an Intel i7 and an ARM Cortex-A9. Experimental results including synthetic benchmarks as well as a real-world control application show that our proposed holistic compilation approach outperforms classic DSEs that are agnostic of QSS as well as a DSE that employs QSS as a post-processing step. Amongst others, we show a case where the compilation approach obtains a speedup of 9.91 x for a 4-core implementation, while a classic DSE only obtains a speedup of 2.12 x.

In this paper, we present a novel model enabling system-level decision making for time-triggered many-core architectures in automotive systems. The proposed application model includes shared data entities that need to be bound to memories during decision making. As a key enabler to our approach, we explicitly separate computation and shared memory communication over a network-on-chip (NoC). To deal with contention on a NoC, we model the necessary basis to implement a time-triggered schedule that guarantees freedom of interference. We compute fundamental design decisions, namely (a) spatial binding, (b) multi-hop routing, and (c) time-triggered scheduling, by a novel coupling of answer set programming (ASP) with satisfiability modulo theories (SMT) solvers. First results of an automotive case study demonstrate the applicability of our method for complex real-world applications.

We propose a dynamic scheduling approach for the concurrent execution of logical actor instances on a single synthesized actor instance. Based on a formal dataflow model of computation, the proposed approach can be applied to a wide range of applications in a model-based design flow. As case-study, we evaluate a bus-cycle-accurate SystemC RTL model based on an InfiniBand network adapter in a PCI Express system.

Abstract Current graphics processing units (GPU) typically offer only a limited number of programmable pipeline stages, whose usage, data flow and topology are mostly fixed. Although a more flexible, custom rendering pipeline can be emulated using the compute functionality of existing GPUs, this approach requires to manage work queues, synchronization, and scheduling in software. In this paper, we present a hardware architecture for a novel, programmable rendering pipeline, which is based on a circulating stream of data and control tokens that are iteratively modified via pattern matching. Our architecture provides light‐weight mechanisms for dynamic thread creation, lock‐free synchronization, and scheduling to support recursion, dynamic shader linkage and custom primitive types. A hardware prototype, running complex examples, demonstrates the improved reconfigurability also the scalability of our graphics architecture.

In this article, an efficient rule-based clustering algorithm for static dataflow subgraphs in a dynamic dataflow graph is presented. The clustered static dataflow actors are quasi-statically scheduled , in such a way that the global performance in terms of latency and throughput is improved compared to a dynamically scheduled execution, while avoiding the introduction of deadlocks as generated by naive static scheduling approaches. The presented clustering algorithm outperforms previously published approaches by a faster computation and more compact representation of the derived quasi-static schedule. This is achieved by a rule-based approach, which avoids an explicit enumeration of the state space. A formal proof of the correctness of the presented clustering approach is given. Experimental results show significant improvements in both, performance and code size, compared to a state-of-the-art clustering algorithm.

Current high-level synthesis tools based on C/C++ offer only limited support for recursion and functions pointers. We present a novel approach for high-level synthesis that represents the program as a term rewriting system. Based on this concept, dynamic creation of threads, parallel recursive tasks and data-dependent branching can be supported in hardware. Complex examples are used to show the effectiveness of our method.

System-level power analysis is commonly used in modern SoC design processes to evaluate power consumption at early design phases. With the increasing variations in manufacturing, the statistical characteristics of parameters are also incorporated in the state-of-the-art methods. However, the spatial correlation between modules still remains as a challenge for system-level statistical power analysis where power models generated from individual modules are used for analysis efficiency or IP protection. In this paper, we propose a novel method to extract variation-aware and correlation-inclusive leakage power models for fast and accurate system-level analysis. For each individual module we generate a power model with different correlation information specified by the module vendor or customer. The local random variables in the power models are replaced by the corresponding ones at system level to reconstruct the correlation between modules so that the accuracy of system-level analysis is guaranteed. Experimental results show that our method are very accurate while being 1000X faster than Monte Carlo simulation and 70X-100X faster than the flattened full chip statistical leakage analysis.

Today, virtual prototypes are often employed for software development early in the design flow. There, high simulation speed may support fast development. So, the acceleration of virtual prototype simulation is important in the early phases of design. To accelerate virtual prototypes, complex prototype simulation can be prevented by exploiting model-specific knowledge. We replace complex event-driven interaction with execution of predefined traces. In particular, we show that, for many dataflow-dominated application models, such accelerating traces may be efficiently determined. Trace determination is based on a novel symbolic search technique. We show that virtual prototypes exploiting such traces may lead to a significant simulation time reduction. The benefits are quantified for the prototype of a SystemC/TLM network packet filter, where traces result in up to 30% simulation acceleration.

Stringent real-time constraints lead to complex search spaces containing only very few or even no valid implementations. Hence, while searching for a valid implementation a substantial amount of time is spent on timing analysis during system synthesis. This paper presents a novel system synthesis approach that efficiently prunes the search space in case real-time constraints are violated. For this purpose, the reason for a constraint violation is analyzed and a deduced encoding removes it permanently from the search space. Thus, the approach is capable of proving both the presence and absence of a correct implementation. The key benefit of the proposed approach stems from its integral support for real-time constraint checking. Its efficiency, however, results from the power of deduction techniques of state-of-the-art Boolean Satisfiability (SAT) solvers. Using a case study from the automotive domain, experiments show that the proposed system synthesis approach is able to find valid implementations where former approaches fail. Moreover, it is up to two orders of magnitude faster compared to a state-of-the-art approach.

In this paper, an efficient embedded software synthesis approach based on a generalized clustering algorithm for static dataflow subgraphs embedded in general dataflow graphs is proposed. The clustered subgraph is quasi-statically scheduled, thus improving performance of the synthesized software in terms of latency and throughput compared to a dynamically scheduled execution. The proposed clustering algorithm outperforms previous approaches by a faster computation and a more compact representation of the derived quasi-static schedules. This is achieved by a rule-based approach, which avoids an explicit enumeration of the state space. Experimental results show significant improvements in both performance and code size when compared to a state-of-the-art clustering algorithm.

State-of-the-art automatic reliability analyses as used in system-level design approaches mainly rely on Binary Decision Diagrams (BDDs) and, thus, face two serious problems: (1) The BDDs exhaust available memory during their construction and/or (2) the final size of the BDDs is, sometimes up to several orders of magnitude, larger than the available memory. The contribution of this paper is twofold: (1) A partitioning-based early quantification technique is presented that aims to keep the size of the BDDs during construction at minimum. (2) A SAT-assisted simulation approach aims to deliver approximated results when exact analysis techniques fail because the final BDDs exhaust available memory. The ability of both methods to accurately analyze larger and more complex systems than known approaches is demonstrated for various test cases.

Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainability improve productivity. However, writing good HLMs for complex systems is still a challenging task. In the context of network controller design, modeling complexity has two major sources: (1) the functionality to handle a single connection, and (2) the number of connections to be handled in parallel. In this paper, we will propose an efficient actor-oriented modeling approach for complex systems by (1) integrating hierarchical FSMs into dynamic dataflow models, and (2) providing new channel types to allow concurrent processing of multiple connections. We will show the applicability of our proposed modeling approach to real-world system designs by presenting results from modeling and simulating a network controller for the Parallel Sysplex architecture used in IBM System z mainframes.

More and more embedded systems provide a multitude of services, implemented by a large number of networked hardware components. In early design phases, dimensioning such complex systems in terms of monetary costs, power consumption, reliability etc. demands for new analysis approaches at the electronic system level. In this paper, two symbolic system level reliability analysis approaches are introduced. First, a formal approach based on Binary Decision Diagrams is presented that allows to calculate exact reliability measures for small to moderate-sized systems. Second, a simulative approach is presented that hybridizes a Monte Carlo simulation with a SAT solver and delivers adequate approximations of the reliability measures for large and complex systems.

Applications in the signal processing domain are often modeled by dataflow graphs. Due to heterogeneous complexity requirements, these graphs contain both dynamic and static dataflow actors. In previous work, we presented a generalized clustering approach for these heterogeneous dataflow graphs in the presence of unbounded buffers. This clustering approach allows the application of static scheduling methodologies for static parts of an application during embedded software generation for multiprocessor systems. It systematically exploits the predictability and efficiency of the static dataflow model to obtain latency and throughput improvements. In this article, we present a generalization of this clustering technique to dataflow graphs with bounded buffers, therefore enabling synthesis for embedded systems without dynamic memory allocation. Furthermore, a case study is given to demonstrate the performance benefits of the approach.

In this work, the focus is put on the behavior of a system in case a fault occurs that disables the system from executing its applications. Instead of executing a random subset of the applications depending on the fault, an approach is presented that optimizes the systems structure and behavior with respect to a possible graceful degradation. It includes a degradation-aware reliability analysis that guides the optimization of the resource allocation and function distribution, and provides data-structures for an efficient online degradation algorithm. Thus, the proposed methodology covers both, the design phase with a structural optimization and the online phase with a behavioral optimization of the system. A case study shows the effectiveness of the proposed approach.

High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special purpose architectures in form of FPGAs or ASICs. However, their efficient implementation is still a challenge, as the design complexity causes exploding development times and costs. This paper presents a new design flow which permits to specify, analyze, and synthesize complex image processing algorithms. A novel buffer requirement analysis allows exploiting possible tradeoffs between required communication memory and computational logic for multi-rate applications. The derived schedule and buffer results are taken into account for resource optimized synthesis of the required hardware accelerators. Application to a multi-resolution filter shows that buffer analysis is possible in less than one second and that scheduling alternatives influence the required communication memory by up to 24% and the computational resources by up to 16%.

A novel design space exploration approach is proposed that enables a concurrent optimization of the topology, the process binding, and the communication routing of a system. Given an application model written in SystemC TLM 2.0, the proposed approach performs a fully automatic optimization by a simultaneous resource allocation, task binding, data mapping, and transaction routing for MPSoC platforms. To cope with the huge complexity of the design space, a transformation of the transaction level model to a graph-based model and symbolic representation that allows multi-objective optimization is presented. Results from optimizing a Motion-JPEG decoder illustrate the effectiveness of the proposed approach.

With ever-increasing system complexities, all major semiconductor roadmaps have identified the need for moving to higher levels of abstraction in order to increase productivity in electronic system design. Most recently, many approaches and tools that claim to realize and support a design process at the so-called electronic system level (ESL) have emerged. However, faced with the vast complexity challenges, in most cases at best, only partial solutions are available. In this paper, we develop and propose a novel classification for ESL synthesis tools, and we will present six different academic approaches in this context. Based on these observations, we can identify such common principles and needs as they are leading toward and are ultimately required for a true ESL synthesis solution, covering the whole design process from specification to implementation for complete systems across hardware and software boundaries.

With increasing design complexity, the gap from ESL (Electronic System Level) design to RTL synthesis becomes more and more crucial to many industrial projects. Although several behavioral synthesis tools exist to automatically generate synthesizable RTL code from C/C++/SystemC-based input descriptions and software generation for embedded processors is automated as well, an efficient ESL synthesis methodology combining both is still missing. This article presents SystemCoDesigner, a novel SystemC-based ESL tool to automatically optimize a hardware/software SoC (System on Chip) implementation with respect to several objectives. Starting from a SystemC behavioral model, SystemCoDesigner automatically extracts the mathematical model, performs a behavioral synthesis step, and explores the multiobjective design space using state-of-the-art multiobjective optimization algorithms. During design space exploration, a single design point is evaluated by simulating highly accurate performance models, which are automatically generated from the SystemC behavioral model and the behavioral synthesis results. Moreover, SystemCoDesigner permits the automatic generation of bit streams for FPGA targets from any previously optimized SoC implementation. Thus SystemCoDesigner is the first fully automated ESL synthesis tool providing a correct-by-construction generation of hardware/software SoC implementations. As a case study, a model of a Motion-JPEG decoder was automatically optimized and implemented using SystemCoDesigner. Several synthesized SoC variants based on this model show different tradeoffs between required hardware costs and achieved system throughput, ranging from software-only solutions to pure hardware implementations that reach real-time performance for QCIF streams on a 50MHz FPGA.

Nowadays many design space exploration tools are based on Multi-Objective Evolutionary Algorithms (MOEAs). Beside the advantages of MOEAs, there is one important drawback as MOEAs might fail in design spaces containing only a few feasible solutions or as they are often afflicted with premature convergence, i.e., the same design points are revisited again and again. Exact methods, especially Pseudo Boolean solvers (PB solvers) seem to be a solution. However, as typical design spaces are multi-objective, there is a need for multi-objective PB solvers. In this paper, we will formalize the problem of design space exploration as multi-objective 0-1 ILP. We will propose (1) a heuristic approach based on PB solvers and (2) a complete multi-objective PB solver based on a backtracking algorithm that incorporates the non-dominance relation from multi-objective optimization and is restricted to linear objective functions. First results from applying our novel multi-objective PB solver to synthetic problems will show its effectiveness in small sized design spaces as well as in large design spaces only containing a few feasible solutions. For non-linear and large problems, the proposed heuristic approach is outperforming common MOEA approaches. Finally, a real world example from the automotive area will emphasize the efficiency of the proposed algorithms.

Meta-heuristic optimization approaches are commonly applied to many discrete optimization problems. Many of these optimization approaches are based on a local search operator like, e.g., the mutate or neighbor operator that are used in evolution strategies or simulated annealing, respectively. However, the straightforward implementations of these operators tend to deliver infeasible solutions in constrained optimization problems leading to a poor convergence. In this paper, a novel scheme for a local search operator for discrete constrained optimization problems is presented. By using a sophisticated methodology incorporating a backtracking-based ILP solver, the local search operator preserves the feasibility also on hard constrained problems. In detail, an implementation of the local serach operator as a feasibility-preserving mutate and neighbor operator is presented. To validate the usability of this approach, scalable discrete constrained testcases are introduced that allow to calculate the expected number of feasible solutions. Thus, the hardness of the testcases can be quantified. Hence, a sound comparison of different optimization methodologies is presented.

SystemCoDesigner is an ESL tool developed at the University of Erlangen-Nuremberg, Germany. SystemCoDesigner offers a fast design space exploration and rapid prototyping of behavioral SystemC models. Together with Forte Design Systems, a fully automated approach was developed by integrating behavioral synthesis into the design flow. Starting from a behavioral SystemC model, hardware accelerators can be generated automatically using Forte Cynthesizer and can be added to the design space. The resulting design space is explored automatically by optimizing several objectives simultaneously using state of the art multi-objective optimization algorithms. As a result, SystemCoDesigner presents optimized hardware/software solutions to the designer who can select any of them for rapid prototyping on an FPGA basis. Thus, SystemCoDesigner bridges the gap from ESL to RTL and increases the confidence in early design decisions.

In this paper, a novel automatic approach for the concurrent topology and routing optimization that achieves a high quality network layout is proposed. This optimization is based on a specialized binary Integer Linear Program (ILP) in combination with a Multi-Objective Evolutionary Algorithm (MOEA). The ILP is formulated such that each solution represents a topology and routing that fulfills all requirements and demands of the network. Thus, in an iterative process, this ILP is solved to obtain feasible networks whereas the MOEA is used for the optimization of multiple even non-linear objectives and ensures a fast convergence towards the optimal solutions. Additionally, a domain specific preprocessing algorithm for the ILP is presented that decreases the problem complexity and, thus, allows to optimize large and complex networks efficiently. The experimental results validate the performance of this methodology on two state-of-the-art prototype automotive networks.

Increasing reliability at a minimum amount of extra cost is a major challenge in todays ECU network design. Considering reliability as an objective already in early design phases has the potential to avoid expensive modifications in later design phases. Hence, there is a need for an appropriate optimization process and efficient analysis techniques to evaluate the found implementations. In this paper, we will show how symbolic techniques can be used to efficiently analyze and optimize such reliable systems. The contribution of this paper is (1) a symbolic reliability analysis that makes use of a partitioned structure function and (2) a symbolic optimization process based on binary ILP solvers. Our case study from the automotive area will show a significant speed-up using our analysis technique. Moreover, our optimization approach is able to offer implementations with considerably improved reliability at no additional costs as well as implementations with reduced costs without decreasing their reliability.

Abstract—In this paper, an efficient embedded software synthesis approach based on a generalized clustering algorithm for static dataflow subgraphs embedded in general dataflow graphs is proposed. The clustered subgraph is quasi-statically scheduled, thus improving performance of the synthesized software in terms of latency and throughput compared to a dynamically scheduled execution. The proposed clustering algorithm outperforms previous approaches by a faster computation and a more compact representation of the derived quasi-static schedules. This is achieved by a rule-based approach, which avoids an explicit enumeration of the state space. Experimental results show significant improvements in both performance and code size when compared to a state-of-the-art clustering algorithm.

This paper presents techniques for generating on-chip buses suitable for dynamically integrating hardware modules into an FPGA-based SoC by partial reconfiguration. The buses permit direct connections of master and slave modules to the bus in combination with a flexible fine-grained module placement and with minimized latency and area overheads. A test system will demonstrate a transfer rate of 800 MB/s while providing an extreme high placement flexibility.

In this paper, we propose a quasi-static scheduling (QSS) method applicable to actor-oriented SystemC designs. QSS determines a schedule where several static schedules are combined in a dynamic schedule to reduce runtime overhead. This is done by performing as much static scheduling as possible at compile time, and only treating data-dependent control flow as runtime decision. Our approach improves known quasi-static approaches in a way that it is directly applicable to real world designs, and has less restrictions on the underlying model. The effectiveness of the approach based on symbolic computation is demonstrated by scheduling a SystemC design of a network packet filter.

Applications in the signal processing domain are often modeled by data flow graphs which contain both dynamic and static data flow actors due to heterogeneous complexity requirements. Thus, the adopted notation to model the actors must be expressive enough to accommodate dynamic data flow actors. On the other hand, treating static data flow actors like dynamic ones hinders design tools in applying domain-specific optimization methods to static parts of the model, e.g., static scheduling. In this paper, we present a general notation and a methodology to classify an actor expressed by means of this notation into the synchronous and cyclo-static dataflow models of computation. This enables the use of a unified descriptive language to express the behavior of actors while still retaining the advantage to apply domain-specific optimization methods to parts of the system. In experiments we could improve both latency and throughput of a general data flow graph application using our proposed automatic classification in combination with a static single-processor scheduling approach by 57%.

For complex optimization problems, several population-based heuristics like Multi-Objective Evolutionary Algorithms have been developed. These algorithms are aiming to deliver sufficiently good solutions in an acceptable time. However, for discrete problems that are restricted by several constraints it is mostly a hard problem to even find a single feasible solution. In these cases, the optimization heuristics typically perform poorly as they mainly focus on searching feasible solutions rather than optimizing the objectives. In this paper, we propose a novel methodology to obtain feasible solutions from constrained discrete problems in population- based optimization heuristics. At this juncture, the constraints have to be converted into the Prepositional Satisfiability Problem (SAT). Obtaining a feasible solution is done by the DPLL algorithm which is the core of most modern SAT solvers. It is shown in detail how this methodology is implemented in Multi-objective Evolutionary Algorithms. The SAT solver is used to obtain feasible solutions from the genetic encoded information on arbitrarily hard solvable problems where common methods like penalty functions or repair strategies are failing. Handmade test cases are used to compare various configurations of the SAT solver. On an industrial example, the proposed methodology is compared to common strategies which are used to obtain feasible solutions.

Progress in reconfigurable hardware technology allows the implementation of complete SoCs in today's FPGAs. In the context design for reliability, software checkpointing is an effective methodology to cope with faults. In this paper, we systematically extend the concept of checkpointing known from software systems to hardware tasks running on reconfigurable devices. We will classify different mechanisms for hardware checkpointing and present formulas for estimating the hardware overhead. Moreover, we will reveal a tool that takes over the burden of modifying hardware modules for checkpointing. Post-synthesis results of applying our methodology to different hardware accelerators will be presented and the results will be compared with the theoretical estimations.

In state of the art hardware-software-co-design flows for FPGA based systems, the hardware-software partitioning problem is solved offline, thus, omitting the great flexibility provided through partial runtime reconfiguration. The decision which functions are best suitable to be implemented in hardware or software, is typically taken with respect to the expected worst case computational demands and certain objectives like power consumption, throughput or cost. However, if these parameters change at runtime, e.g., due to environmental changes, traditional designed systems lack to adapt to the new conditions, because the hardware-software partitioning is static. This paper systematically presents a new methodology that allows changing the implementation style of tasks at runtime by hardware-software morphing. Based on a formal model, how morphing can be performed without loosing internal states was demonstrated. Moreover, results from applying this methodology were demonstrated to a 16-tap FIR filter.

Even though transaction level modeling (TLM) with SystemC is widely being used and despite the existence of several formal models for TLM, there is no generally accepted definition of what a transaction is and how exactly to define transaction level modeling. The key contribution of this paper is the analysis of TLM characteristics and a definition of transactions resulting in better analyzability of TLMs. For this purpose, transactions are restricted to the ACID properties (atomicity, consistency, isolation, and durability) known from database systems. Based on these results, a finite state machine model well suited for formal analysis was proposed along with an implementation of the basic concepts in SystemC.

We propose a framework, called virtual processing components (VPC) that permits the modeling and simulation of multiple processors running arbitrary scheduling strategies in SystemC. The granularity is given by task accuracy that guarantees a small simulation overhead

Sliding window algorithms are fundamental parts of each image processing system. Especially those belonging to the class of static algorithms offer various possibilities for analysis and optimization. Only if this potential is exploited, a high level synthesis of such algorithms will lead to efficient implementations. Such an analysis relies on an efficient representation by a well-defined model of computation. It must abstract important properties of sliding windows as for instance the relation between input and output data as well as the required buffer space. In this paper, a corresponding static model of computation for sliding window algorithms is elaborated, called windowed synchronous data flow (WSDF). Its main focus lies on applications with two or more dimensions. Furthermore, the WSDF balance equation is derived allowing to verify bounded token accumulation during execution

The task of automatic design space exploration of heterogeneous multi-processor systems is often tackled with evolutionary algorithms. In this paper, we propose a novel approach in combining evolutionary algorithms with symbolic techniques in order to improve the convergence speed. The main idea is to guide the search towards the feasible region by utilizing symbolic techniques. We present experimental results showing the advantages of our novel approach, especially when the search space contains only few feasible solutions, what is often the case when designing heterogeneous multi-processor systems.

There is trend towards networked and distributed hardware reconfigurable systems, complicating the design process at the system-level. This paper will provide a solution to the problem of design space exploration for such embedded systems of the next generation. We will show the problems occurring while exploring the design space at the system-level, leading to new properties for valid implementations. The novelty of this approach lies in the support of explicit communication modeling and time-multiplexed architecture modeling in a single model. The proposed design space exploration is based on Evolutionary Algorithms and a new slack-based list scheduler.

Today's embedded systems are typically distributed and more often confronted with time-varying demands. Existing methodologies that optimize the partitioning of computational tasks to hardware (HW) and software (SW) at compile-time become obsolete or inefficient in this context as the optimal use of existing resources cannot be foreseen. Here, we investigate a discrete iterative algorithm that balances the load of a HW/SW partition online: Once there are changing computational demands, the system will dynamically assign tasks to reconfigurable HW or SW resources and migrates tasks to other nodes if necessary. For this purpose an Evolutionary Algorithm combined with a discrete version of a diffusion algorithm is presented. Concerning the diffusion algorithm, we will show theoretically and by experiment that our version is run-time optimal in a linear number of steps.

Particle swarm optimization (PSO) has successfully been applied to many optimization problems. One particularly interesting aspect of these algorithms is to study the communication behavior of the particles. Often, a neighborhood topology is defined a priori and used throughout the optimization run. However, the cost of communication between particles has not been analyzed up to now. In this paper, we will propose a novel algorithm called DAPSO (distributed archives PSO) that makes use of stationary archives to establish indirect communication architecture in the swarms. Moreover, we provide analytical results of the required communication energy in such a scenario. This might be especially important in robot swarms and sensor networks. The applicability of our new methodology will be shown on some selected test cases.

In this paper, we propose a distributed online HW/SW-partitioning strategy for increasing fault tolerance in HW/SW-reconfigurable networked systems. It consists of a HW/SW bipartitioning heuristic and a dynamic load balancing algorithm.

This paper will propose a novel approach in combining Evolutionary Algorithms with symbolic techniques in order to improve the convergence of the algorithm in the presence of large search spaces containing only few feasible solutions. Such problems can be encountered in many real-world applications. Here, we will use the example of design space exploration of embedded systems to illustrate the benefits of our approach. The main idea is to integrate symbolic techniques into the Evolutionary Algorithm to guide the search towards the feasible region. We will present experimental results showing the advantages of our novel approach.

In this paper, we propose an approach for the synthesis of heterogeneous (embedded) systems, while exploiting a hierarchical problem structure. Particular to our approach is that we explore the set of so-called Pareto-optimal solutions, i.e., optimizing multiple objectives simultaneously. Since system complexity grows steadily leading to giant search spaces which demand for new strategies in design space exploration, we propose Pareto-Front Arithmetics (PFA) using results of subsystems to construct implementations of the top-level system. This way, we are able to reduce the exploration time dramatically. An example of an MPEG4 coder is used to show the benefit of this approach in real-life applications.

With the term flexibility, we introduce a new design dimension of an embedded system that quantitatively characterizes its feasibility in implementing not only one, but possibly several alternative behaviors. This is important when designing systems that may adapt their behavior during operation, e.g., due to new environmental conditions, or when dimensioning a platform-based system that must implement a set of different behaviors. A hierarchical graph model is introduced that allows us to model flexibility and cost of a system formally. Based on this model, an efficient exploration algorithm to find the optimal flexibility/cost-tradeoff-curve of a system using the example of the design of a family of set-top boxes is proposed.