Protecting the integrity of hardware against invasive tampering within the supply chain is critical to ensuring overall system resilience, reliability, and trustworthiness. As electronic systems become increasingly complex and globally distributed, the risk of malicious modifications or unauthorized alterations to hardware components continues to grow. In this survey, we provide a comprehensive exploration of detection and mitigation strategies for invasive hardware tampering across multiple levels of the hardware stack. We consider threats at various granularities–from individual on-board integrated circuits (ICs), to Printed Circuit Board Assemblies (PCBAs), and up to complete end-user devices. Our focus centers on three primary categories of invasive tampering: hardware Trojans, counterfeit components, and physical manipulations. A key emphasis of this survey is on hardware security techniques that leverage alterations in electrical characteristics induced by tampering. These include changes in power delivery network (PDN), signal trace, and other low-level electrical pathways. Such variations often serve as sensitive indicators of physical intrusions or modifications and are particularly useful for monitoring hardware integrity throughout its lifecycle–from manufacturing and deployment to maintenance and eventual decommissioning. We examine both golden-reference-based and golden-free detection approaches, highlighting their operational principles, design tradeoffs, and applicability in different threat scenarios. Furthermore, we survey evaluation methodologies and metrics used to assess the effectiveness, scalability, and robustness of these techniques. This article aims at providing a unified and up-to-date overview of detection research framework based on electrical characteristic variation, offering critical insights for researchers and practitioners working to safeguard hardware systems against invasive tampering and supply chain threats.

Over the past decade, as GPUs have evolved to achieve higher computational performance, their power density has also accelerated. Consequently, improving energy efficiency and reducing power consumption has become critically important. Dynamic voltage and frequency scaling (DVFS) is an effective technique for enhancing energy efficiency. With the advent of integrated voltage regulators, DVFS can now operate on microsecond$(\boldsymbol{\mu}\mathbf{s})$timescales. However, developing a practical and effective strategy to guide rapid DVFS remains a significant challenge. This paper proposes a supervised and self-calibrated machine learning framework (SSMDVFS) to guide microsecond-scale GPU voltage and frequency scaling. This framework features an end-to-end design that encompasses data generation, neural network model design, training, compression, and final runtime calibration. Unlike analytical models, which struggle to accurately represent GPU architectures, and reinforcement learning approaches, which can be challenging to converge during runtime, the SSMDVFS offers a practical solution for guiding microsecond-scale voltage and frequency scaling. Experimental results demonstrate that the proposed framework improves energy-delay product (EDP) by 11.09% and outperforms analytical models and reinforcement learning approaches by 13.17% and 36.80 %, respectively.

With the popularity of virtualization technology, ensuring reliable I/O operations with timing constraints in virtual environments becomes increasingly critical. Timing-predictable virtual I/O enhances the responsiveness and efficiency of virtualized systems, facilitating their seamless integration into time-critical applications such as industrial automation and robotics. Its significance lies in meeting rigorous performance standards, minimizing latency, and consistently delivering predictable I/O performance. As a result, virtual machines can effectively support mission-critical and time-sensitive workloads. However, due to the complicated system architecture, the I/O operations in virtualization face competition from tasks within the same virtual machine and those in different virtual machines who share the same host machine. This study presents RT-VirtIO, a practical approach to provide predictable real-time I/O operations. RT-VirtIO addresses the challenges associated with lengthy data paths and complex resource management. Through early-stage characterization, this study identifies key factors contributing to poor I/O real-time performance and then builds an analytical model and a learning-based data-driven model to predict the tail I/O latency. Leveraging these two models, RT-VirtIO effectively captures these dynamics, enabling the development of a general and applicable optimization framework. Experimental results demonstrate that RT-VirtIO significantly improves real-time performance in virtual environments (by 20.07% ~ 30.90%) without necessitating hardware modifications, which exhibit promising applicability across a broader range of scenarios.