Graph Neural Network (GNN) is a powerful tool for automatically learning and predicting features of graph data. To study the explainability of a given GNN model, several methods have been proposed, including GNNExplainer, CF2, and SubgraphX. Unfortunately, these methods lack sufficient consideration on the connectedness of the output. The challenge is that the connectedness of a graph is difficult to optimize within the framework of Graph Learning (GL), because it is defined as a discrete number of the connected components of the graph, whereas GL uses continuous optimization (e.g., gradient descent).To address this issue, this article proposes a novel Continuous Representation of Connectedness (CRoC) with time complexity of O(n3), improving from a previous study Connected-CF2. Moreover, an optimizable framework CRoCExplainer is given to integrate both reasoning and connectedness for a given GNN model. Empirical studies show that CRoCExplainer outperforms the state-of-the-art methods in interpretability and efficiency.

Coplanar Waveguides (CPW) are ideally suited for coherently interfacing resonators with superconducting qubits. However, integrating CPWs with circuit elements on quantum chips involves curvature and discontinuities of the central conductors and corresponding ground planes, which may generate undesired parasitic modes. Experiments have demonstrated that air-bridges can effectively suppress this unwanted effect. Nevertheless, as quantum processors increase in size, manual air-bridge placement on the chip layout becomes increasingly time-consuming and error-prone. Automation of this process is therefore highly desirable, especially when the center line (channel) of the CPWs is not pre-established. In this paper we propose a parametric EDA method for coplanar waveguide channel identification and air-bridge construction in quantum chips. Our approach applies to both separated and full-package air-bridges and scales efficiently, with running time linear in the number of points and quadratic in the number of arcs in the corresponding chip layout. We evaluate our approach on a set of open-source quantum chip layouts, generating air-bridges in times ranging from 0.05 to 0.5 seconds—a practical speedup of over 10,000 times compared to manual generation. Furthermore, We propose two original quantitative metrics, accuracy and overlap, and verify that our method yields reliable results, producing air-bridges in the required shapes and locations. We fabricate a 13-qubit chip using our method for air-bridge placement, and observe excellent performance with minimal microwave and flux crosstalk. This research enables rapid generation of air-bridges when CPW channels are not pre-specified, paving the way for more flexible, automated, and modular design of superconducting quantum EDA.