VLDB 2026 Research / reviewers in the wild / expert
Rhys Gretsch
dblp:373/5492
· DBLP profile ↗
2ranked-venue papers
2as first author
2since 2021 · last 2025
0009-0004-1416-5532ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author · 2 since 2021Software engineering, systems software and programming languages · 2 · 2 first-author · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Emerging computing paradigms · 52% Hardware accelerators and domain-specific architectures · 31% Memory systems · 17% | |
| Artificial intelligence
1 paper |
Deep learning architectures and training · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator |
0.9 | 1 | 2025 | Single Spike Artificial Neural Networks · ISCA 2025 |
Emerging computing paradigms
neuromorphic computing |
0.9 | 1 | 2025 | Single Spike Artificial Neural Networks · ISCA 2025 |
Memory systems
processing-in-memory |
0.9 | 1 | 2025 | Single Spike Artificial Neural Networks · ISCA 2025 |
Emerging computing paradigms › neuromorphic computing
spiking neural network |
0.9 | 1 | 2025 | Single Spike Artificial Neural Networks · ISCA 2025 |
Emerging computing paradigms
approximate computing |
0.8 | 1 | 2024 | Energy Efficient Convolutions with Temporal Arithmetic · ASPLOS (2) 2024 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator › convolution acceleration
convolution accelerator |
0.8 | 1 | 2024 | Energy Efficient Convolutions with Temporal Arithmetic · ASPLOS (2) 2024 |
Machine learning › Deep learning architectures and training
neural network inference |
0.3 | 1 | 2025 | Single Spike Artificial Neural Networks · ISCA 2025 |
Emerging computing paradigms › approximate and stochastic computing
stochastic computing |
0.2 | 1 | 2024 | Energy Efficient Convolutions with Temporal Arithmetic · ASPLOS (2) 2024 |
Methods — techniques the papers use, named apart from their topics
temporal encoding · 0.8multiply-accumulate · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Single Spike Artificial Neural NetworksabstractSpiking neural networks (SNNs) circumvent the need for large scale arithmetic using techniques inspired by biology.However, SNNs are designed with fundamentally different algorithms from ANNs, which have benefited from a rich history of theoretical advances and an increasingly mature software stack.In this paper we explore the potential of a new technique that lies between these two approaches, one that can leverage the software and system level optimizations of ANNs while utilizing biologically inspired circuits for energy efficient computation.The resulting hardware represents the traditional weight of an ANN as nothing more than a delay element and the degree of activation as nothing more than arrival time of a digital signal.Building on these fundamental operations, we can implement complete ANNs through several innovations: spatial and temporal reuse that facilitates classical dataflows, reducing memory system demands for ANN temporal operations; a new noise-tolerant temporal summation operation; novel hybrid digital/temporal memories; and the integration of temporal memory circuits for shepherding inter-layer activations.Using the MLPerf Tiny benchmark suite, we demonstrate how several architectural parameters can impact inference accuracy, that our proposed systolic array can provide 11× better energy consumption with a 4× improvement in latency compared to SNNs, and when equipped with temporal memories provides 3.5× improvements in energy compared to the most aggressive 8-bit digital systolic arrays. Rhys Gretsch, Michael Beyeler, Jeremy Lau, Timothy Sherwood |
ISCA | 1 |
| 2024 | Energy Efficient Convolutions with Temporal ArithmeticabstractConvolution is an important operation at the heart of many applications, including image processing, object detection, and neural networks. While data movement and coordination operations continue to be important areas for optimization in general-purpose architectures, for computation fused with sensor operation, the underlying multiply-accumulate (MAC) operations dominate power consumption. Non-traditional data encoding has been shown to reduce the energy consumption of this arithmetic, with options including everything from reduced-precision floating point to fully stochastic operation, but all of these approaches start with the assumption that a complete analog-to-digital conversion (ADC) has already been done for each pixel. While analog-to-time converters have been shown to use less energy, arithmetically manipulating temporally encoded signals beyond simple min, max, and delay operations has not previously been possible, meaning operations such as convolution have been out of reach. In this paper we show that arithmetic manipulation of temporally encoded signals is possible, practical to implement, and extremely energy efficient. Rhys Gretsch, Peiyang Song 0002, Advait Madhavan, Jeremy Lau, Timothy Sherwood |
ASPLOS (2) | 1 |