A modified self-biased$\beta $-multiplier-based current reference (CR) circuit is proposed for ultralow-power Internet of Things (IoT) application and is realized without any resistors, bipolar junction transistors (BJTs), or operational amplifiers (OPAs). The proposed CR circuit directly generates the reference current from a modified$\beta $-multiplier, which is biased by a stacked diode-connected MOS transistor (SDMT)-based compensated through a complementary-to-absolute temperature (CTAT) voltage. The proposed CR is implemented in a standard 0.18-$\mu $m CMOS process with an active area of 0.0069 mm2and almost all transistors operate in the subthreshold region. Measurement results show that the temperature coefficient (TC) of the CR is 248 ppm/°C in a temperature range from$- 40~^{\circ }$C to$125~^{\circ }$C. The proposed CR exhibits a line sensitivity (LS) of 0.33%/V within the supply voltage range of 0.8–1.4 V. The output of the CR at room temperature ($25~^{\circ }$C) is 1.84 nA with a power consumption of 3.7 nW.

This article presents an analog delay-locked loop (DLL) designed for high-precision measurement applications, featuring low static phase offset (SPO) and fast locking speed, such as time-to-digital converters (TDCs) and analog-to-digital converters (ADCs). A large gain and dead-zone free phase detector (PD) is proposed. When the DLL reaches the locked state, the phase error between the two input signals of the PD can be reduced to 0.53 ps (0.095°), which has an 18-time improvement compared to the conventional DLL. Therefore, the SPO of the entire DLL can be effectively reduced to be less than 0.87 ps. Furthermore, the auxiliary circuit, consisting of a large phase difference detector (LPDD) and fast-adjusting branches (FABs), accelerates the DLL’s locking process to 42 clock cycles and improves the locking speed by 4.1 times. Designed by a standard 180 nm CMOS technology, the DLL occupies an area of$106.1\times 93.3~\mu $m. It achieves low power consumption of 1.89mW at 500 MHz, and the root mean square (rms) jitter and P-P jitter are 1.01 and 6.26 ps, respectively.

This article proposes a fully differential ten-bit energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC) for wearable 12-lead electrocardiogram (ECG) acquisition system. The proposed ADC structure generates two bypass windows through capacitor splitting technique, which can skip unnecessary quantization steps. The judgment module of bypass windows only requires anXORgate. By introducing redundant capacitors to participate in quantization, the total capacitance value is reduced by half. The proposed SAR ADC is fabricated using a standard 180-nm CMOS process. The measurement results show that it can achieve an effective number of bits (ENOBs) of 9.38 bits and a spurious-free dynamic range (SFDR) of 76.71 dB with a supply voltage of 0.6 V at a sampling rate ($\text{F}_{\mathrm {S}}$) of 6.94 kS/s. The power consumption is 15.61 nW when subjected to a 1.17-$\text{V}_{\mathrm {PP}}~3.45$-kHz sinusoidal input, resulting in a figure of merit (FoM) of 3.38 fJ/conv.-step. The average power consumption for quantizing 12-lead ECG signals is approximately 12.66 nW, demonstrating the ability to achieve ultralow-power quantization of ECG signals.

This paper presents a high precision bandgap reference using high-order curvature compensation to achieve good temperature coefficients over a wide operating range. The proposed compensation circuit employs currents with optimized temperature coefficients to minimize the temperature drift of the output voltage. The proposed bandgap reference is designed using a standard 0.18μm CMOS process. The simulation results demonstrate that the proposed bandgap reference achieved a 1.02ppm/°C from -40°C to 125°C with a supply voltage of 3.3V. With the proposed high-order curvature compensation schemes, the bandgap reference circuit can achieve a start-up time of 7μs and a 85.5dB PSRR at 100Hz. The reference voltage is 1.066V with the precision line sensitivity (LS) of 0.011%/V for supply voltages between 2V and 5V.

A transconductance amplifier with low-Gmis indispensable for applications that acquire low-frequency bioelectric signals. This paper proposes a subthreshold bootstrapped low-Gmtransconductor based on body-input. The input topology of the transconductor consists of two transistors with body inputs and a source degeneration resistor. The outputs of the two transistors are connected to the resistor to bootstrap the voltages at these terminals and increase the equivalent resistance. An area-efficient serial-parallel current division network is further adopted to reduce the Gmof the transconductor. Meanwhile, programming the bias voltage can tune the Gmvalue. The circuit is designed using a standard 0.18 μm CMOS process. Simulations verify the characteristics of the proposed transconductor. The post-layout simulation results show that the transconductor’s Gmvalue is tunable within a range of a few hundred pS. The minimum achievable Gmis 12.3 pS, and the linear input range is ±150 mV. The input referred noise power spectral density (PSD) of the transconductor is 13.7 μV/√Hz. It consumes 0.816 nW of power with 0.8 V supply voltage and occupies an area of 0.0057 mm2.