The demand for next-generation flexible electronics (FE) is rapidly increasing, especially in cost-sensitive consumer markets such as smart packaging, smart bandages, drug delivery systems, RFID tags, and wearable devices. Traditional silicon based electronics, constrained by high manufacturing costs and rigid form-factor, are inadequate for these emerging applications. However, the lack of rigid packaging in FE, combined with their complex and variable operating conditions, makes them more susceptible to thermal issues, therby leading to significant performance degradation, abnormal heating, and potential risks to device reliability and safety. To address these thermal challenges, we propose a novel approach to design thermal-resilient (TR) flexible analog neuromorphic circuits (f-NCs) based on amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). This cross-layer approach integrates TR circuit design for activation functions (AFs) and evolutionary algorithm (EA) based TR training using Neural Architecture Search (NAS) optimizing both the circuit-level thermal resilience and the architecture level training, ensuring robust performance of $\boldsymbol{f}$-NCs under varying thermal conditions. Experiments on 13 benchmark datasets demonstrate that thermal variations result in up to its $\mathbf{5 0. 3} \boldsymbol{\%}$ accuracy loss and the proposed evolutionary algorithm-based thermal-resilient training fully recovers this accuracy at the expense of $1.81 \times$ area and $1.39 \times$ power overhead.

Printed electronics (PE) enable lightweight, flexible, and low-cost devices for the Internet of Things (IoT) and wearable applications. Compared to conventional silicon-based electronics, PE trades peak performance for advantages in cost efficiency, mechanical flexibility, and large-area fabrication. However, its manufacturing processes remain unreliable and are prone to structural defects and variation due to inherent limited control in additive manufacturing. Printed neuromorphic circuits (pNCs) leverage the benefits of PE for on-demand analog edge computation in target applications but remain vulnerable to such defects. Diagnostic testing is therefore essential not only for detection but also for localizing faults to specific subcircuits and regions in the layout, a step critical for guiding yield improvement and reducing the cost of downstream inspection. We propose a diagnostic test pattern generation (DTPG) framework for fault localization in pNCs under black-box access. While ATPG is typically formulated as an optimization problem for fault detection, our approach extends this formulation by explicitly optimizing for fault distinguishability. On ten UCI datasets, the framework achieves up to 20.7% higher diagnostic coverage with a reduction of up to 3.6 times the number of undetectable subcircuits than detection-only test sets, while constraining the number of patterns to reduce storage overhead. These results demonstrate effective fault localization and establish a foundation for finer-grained, component-level diagnosis in future work.

With the rising demand for ultra-low-cost and flexible electronics in applications like smart packaging and wearable health monitoring, printed electronics provide an affordable, adaptable, and customizable alternative to conventional silicon. However, these systems often rely on printed batteries or energy harvesters with limited power capacity, making strict power budgets critical. Printed neuromorphic circuits (pNCs) are promising for their analog signal processing, reduced circuit complexity, and energy efficiency in low-power environments. Nonetheless, maintaining robust performance under strict power constraints remains challenging, necessitating advanced optimization techniques. In this work, we propose an augmented Lagrangian approach to enforce task-specific power constraints in pNCs, validated across 13 benchmark datasets. Our method preserves accuracy within strict power budgets while achieving Pareto-optimal power-accuracy trade-offs in a single training run. In contrast, the penalty-based method, which serves as the baseline, requires up to 150 runs per dataset to generate the Pareto front. For low-power scenarios ($\approx 20 \%$ of the original power), our method demonstrates a $52 \times$ improvement in accuracy-to-power ratio over the baseline. At higher power budgets $(\approx 80 \%$ of the original power), it achieves a $59 \times$ improvement, maintaining competitive performance. Experimental results demonstrate that our approach achieves $\mathbf{8 1. 8 2 \%}$ accuracy with p-tanh activation function (AF) at high power budgets and excels with p-Clipped_ReLU AF under low power constraints. This highlights the computational efficiency and effectiveness of our approach for power-constrained circuit design.

The rise of the Internet of Things demands flexible, biocompatible, and cost-effective devices. Printed electronics provide a solution through low-cost and on-demand additive manufacturing on flexible substrates, making them ideal for IoT applications. However, variations in additive manufacturing processes pose challenges for reliable circuit fabrication. Adapting neuromorphic computing to printed electronics could address these issues. Printed neuromorphic circuits offer robust computational capabilities for near-sensor processing in IoT. One limitation of existing printed neuromorphic circuits is their inability to process temporal sensory inputs. To address this, integrating temporal components in printed neuromorphic circuit architectures enables the effective processing of time-series sensory data. Printed neuromorphic circuits face challenges from manufacturing variations such as ink dispersion, sensor noise, and temporal fluctuations, especially when processing temporal data and using time-dependent components like capacitors. To mitigate these challenges, we propose robustness-aware temporal processing neuromorphic circuits with low-pass second-order learnable filters (SO-LF). This approach integrates variation awareness by considering the variation potential of component values during training and using data augmentation to enhance adaptability against physical and sensor data variations. Simulations on 15 benchmark time-series datasets show our circuit effectively handles noisy temporal information under 10% process variations, achieving an average accuracy and power improvement of ≈24.7% and ≈91% respectively compared to models lacking variation with ≈1.9×more devices.

Biologically-inspired Spiking Neural Networks (SNNs) have emerged as a promising avenue toward energy-efficient neuromorphic computing, particularly in edge applications such as soft robotics, wearable health monitors, and IoT devices. Printed Electronics (PE), offering advantages of ultra-low cost fabrication and mechanical flexibility, present a viable platform to realize such neuromorphic systems at scale. However, designing adaptable and efficient spiking circuits that meet the unique constraints of PE applications remains a challenge. To address this, we propose a novel analog spiking neuromorphic circuit with a learnable spike generator (LSG). Unlike fixed-threshold models, our generator adapts spike timing dynamics during training, enabling better task-specific performance. To optimize for ultra-low power consumption on resource-constrained platforms, we further introduce a robustness-aware training framework that further minimizes the energy consumption adaptively. Simulation results across 13 benchmarks demonstrate an average 57.6% power reduction for the LSG while improving the average classification accuracy by 8%, area and energy reduction by 89% and 28.7% respectively compared to the state-of-the-art printed analog spiking neural networks (P-SNNs).

The demand for next-generation flexible electronics in applications like smart packaging and smart bandages has driven the need for cost-effective solutions. Traditional silicon-based electronics struggle with high costs and rigidity, making them unsuitable for these emerging markets. In this regard, additive printed electronics (PE) offer a viable alternative with their flexibility and ultra-low-cost manufacturing. printed analog neuromorphic circuits (pNCs) are well-suited for these target applications, especially for classification tasks, as their low device count can efficiently meet the needs of the technology. However, low-cost additive manufacturing comes with higher defect rates, such as misprints, broken connections, and defective components, posing significant challenges to the reliability of printed circuits. This article presents a novel co-design of training algorithm and hardware for fault-tolerant pNCs using fault-aware training (FAT). The proposed method introduces a fault-tolerant version of printed nonlinear transformation circuits, combined with a bespoke training process that selects different types of printed activation functions (AFs) for different neurons to optimize both fault endurance and hardware costs. Experiments on benchmark datasets demonstrate an improvement in the accuracy of fault-tolerant (FT) pNCs from 62.1% to 79.4% under a 10% fault rate. Moreover, combining both normal and fault-tolerant versions of activation functions (AFs) using gumble-softmax distribution shows an acceptable accuracy drop with an average reduction in power and area of 54.5% and 6.54%, respectively, while reducing the training time significantly by 56.2%, compared to only using FT-AFs.

Complex systems are subject to various hardware and software defects and faults through the entire design and deployment lifecycle. Many of such defects originate at the electrical or circuit levels, but manifest as functional failures in the field. In this study, we present a methodology for embedding and employing software-controlled runtime variation and degradation sensors on a RISC-V SoC to enable system-level and functional testing in the field. We demonstrate the effectiveness of the entire platform through an FPGA implementation. Delay defects and path degradations are emulated by injecting artificial delay elements into the critical path of a specific instruction. We also emulate the effect of workload-induced runtime stress with tunable software-controlled power wasters. Combining various sensors, we show that transient fluctuations, which are caused by temperature or workload, can be effectively separated from persistent delay increase, which is caused by latent manufacturing defects or aging.

The market demand for next-generation flexible electronics is experiencing a significant upsurge, particularly in cost-sensitive consumer applications like smart packaging and smart bandages. These products are beyond the reach of traditional silicon-based electronics due to their high production cost and rigid form factor. Printed electronics (PE), with its adaptable and ultra-low-cost solutions, essentially meet the unique needs of these emerging application areas. This work presents a novel approach using an evolutionary algorithm (EA) to design highly bespoke printed analog neuromorphic circuits (pNCs) offering robustness against variability inherent in the printing process. By leveraging this algorithm and designing robust activation circuits, not only the resistances (weights) in the crossbar and parameters in the activation circuits, but also the types of nonlinear circuits (i.e., functional forms of activation functions) as well as the circuit topologies (neural architecture) can be learned to enhance the circuit robustness against printing variations. Experiments on 13 benchmark datasets demonstrate that, compared to the baseline, the proposed methodology can further outperform the normalized classification error rate by ≈ 55.38% and ≈ 25.11% under high-precision (±5%) and low-precision (±10%) printing scenarios, respectively. Moreover, the algorithm suggests the ReLU as the most robust activation function (AF) circuit family with only ≈ 21% susceptible to low precision (±10%) printing variation.