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Keiho Akiyama

dblp:38/1057 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
aliasing reduction		 0.011991
A method of reducing aliasing in a built-in self-test environment · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Electronic design automation › hardware verification and test › design for testability
built-in self-test		 0.011991
A method of reducing aliasing in a built-in self-test environment · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Electronic design automation
hardware verification and test		 0.011991
A method of reducing aliasing in a built-in self-test environment · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Electronic design automation › hardware verification and test
test generation		 0.011991
A method of reducing aliasing in a built-in self-test environment · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Electronic design automation › hardware verification and test › fault testing
transition count testing		 0.011991
A method of reducing aliasing in a built-in self-test environment · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991

Methods — techniques the papers use, named apart from their topics

transition count testing · 0.0pseudo-exhaustive testing · 0.0
YearPublicationVenuePosition
1991 A method of reducing aliasing in a built-in self-test environment
abstract
A method of reducing aliasing in built-in self-test of VLSI circuits is proposed. The method is based on the use of transition count testing. A new formulation of the problem is given in terms of finding a test generator as opposed to solving the problem at the data compaction end. An algorithm is proposed which can be used to find a counter-based test pattern generator. This test generator tests a circuit exhaustively or pseudo-exhaustively so that the aliasing is reduced substantially provided the data compactor used is a transition counter. Experimental results are presented to substantiate these claims.>
Keiho Akiyama, Kewal K. Saluja
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1