Demo Data from VLDB 2026 / reviewers in the wild / expert
A. Feller
dblp:38/10971
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 1983
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
logic synthesis |
0.0 | 1 | 1983 | APSS: An automatic PLA synthesis system · DAC 1983 |
Electronic design automation › logic synthesis › programmable logic array
programmable logic array design |
0.0 | 1 | 1983 | APSS: An automatic PLA synthesis system · DAC 1983 |
Electronic design automation
physical design |
0.0 | 1 | 1976 | Automatic layout of low-cost quick-turnaround random-logic custom LSI devices · DAC 1976 |
Electronic design automation › physical design
placement and routing |
0.0 | 1 | 1976 | Automatic layout of low-cost quick-turnaround random-logic custom LSI devices · DAC 1976 |
Electronic design automation › physical design › cell layout
standard cell layout |
0.0 | 1 | 1976 | Automatic layout of low-cost quick-turnaround random-logic custom LSI devices · DAC 1976 |
Methods — techniques the papers use, named apart from their topics
multiport placement and routing · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1983 | APSS: An automatic PLA synthesis system
M. W. Stebnisky, M. J. McGinnis, Joseph C. Werbickas, Rathin Putatunda, A. Feller |
DAC | 5 |
| 1976 | Automatic layout of low-cost quick-turnaround random-logic custom LSI devicesabstractThis paper discusses the application of the RCA-developed standard cell approach for generating low-cost, quick-turnaround random-logic LSI arrays using automatic placement and routing computer programs. Originally developed with government support1 for two-phase PMOS dynamic logic in 1967, the programs have been expanded to include many technologies2,3 and have gone through extensive evolutionary and revolutionary changes during the past 10 years. They have been used extensively by various government agencies and by many industrial concerns, including RCA. Perhaps a 1000 arrays using the PMOS, CMOS, and CMOS-SOS technologies have been generated using these programs and their derivations in the various companies. Within RCA more than 200 LSI arrays have been generated by these technologies.This paper describes these techniques and discusses various LSI circuits that demonstrate the operation of these programs, as well as the major changes that have occurred in them during the past 10 years. The applications include large LSI systems in addition to individual LSI circuit applications.The Multiport Placement and Routing Algorithm, which is introduced for the first time, demonstrates several CMOS-SOS LSI circuits (including the fastest and most powerful microprocessor yet designed) which show densities comparable to handcrafted custom LSI chips. A. Feller |
DAC | 1 |