Demo Data from VLDB 2026 / reviewers in the wild / expert
Shruti Patil
dblp:38/3206
· DBLP profile ↗
16ranked-venue papers
4as first author
6since 2021 · last 2026
0000-0002-4903-1540ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 8 · 3 first-authorArtificial intelligence and machine learning · 5 · 4 since 2021Software engineering, systems software and programming languages · 3 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 2 · 2 since 2021Computer networks · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Emerging computing paradigms · 100% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization › domain-specific compilation
quantum compilation |
0.2 | 1 | 2015 | Compiler Management of Communication and Parallelism for Quantum Computation · ASPLOS 2015 |
Emerging computing paradigms
quantum computer architecture |
0.2 | 1 | 2015 | Compiler Management of Communication and Parallelism for Quantum Computation · ASPLOS 2015 |
Emerging computing paradigms › quantum computer architecture
quantum error correction |
0.1 | 1 | 2015 | Compiler Management of Communication and Parallelism for Quantum Computation · ASPLOS 2015 |
Methods — techniques the papers use, named apart from their topics
SIMD scheduling · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Meta-learning ensemble for emotion detection in conversational textabstractAbstract Advances in Artificial Intelligence (AI), Machine Learning (ML), and Deep Learning (DL) are enabling machines to emulate human-like behaviors. In the context of social computing, lifelike characters are crucial as they facilitate natural and intuitive interactions between humans and computers. Chatbots, a key application of such technologies, are computer programs that use Natural Language Processing (NLP) to engage in text-based conversations. They are widely used in customer service and other domains, but the challenge lies in designing chatbots that feel more human to enhance user engagement. Research has shown that incorporating emotions into chatbots is critical for achieving this goal. Effective emotion recognition systems must be able to process real-time text interactions, understand users’ sentiments on various topics, address their concerns, and respond appropriately based on the detected emotions. This paper proposes a meta-learning ensemble approach for text-based emotion detection in conversational data. The proposed method combines the outputs of multiple well-established machine learning algorithms to improve accuracy in recognizing emotions in text. A comparative analysis was conducted on two conversational datasets, demonstrating that the meta-learning ensemble method outperforms individual machine learning algorithms on both datasets. The proposed approach achieved 73% classification accuracy on the Empathetic Dialogues dataset, while on the EmoContext dataset, it achieved 95.1% classification accuracy, significantly outperforming results over individual machine learning algorithms. The conclusions demonstrate that utilizing a meta-learner for model fusion successfully leverages the advantages of separate algorithms while alleviating their intrinsic shortcomings, resulting in enhanced overall performance. Sheetal Kusal, Shruti Patil, Aasheer Peerbhai, Ketan Kotecha, Ganeshsree Selvachandran, Ajith Abraham |
Neural Comput. Appl. | 2 |
| 2025 | Multi-head attention transformer and Bayesian inference recommendation engine-based blade icing detection framework for wind turbinesabstractAbstract Icing accumulation on wind turbine blades significantly diminishes power output and revenue generation. Traditional icing detection methods, including sensor-based and model-based approaches, heavily rely on domain knowledge, contrasting with data-centric methods. However, a balanced distribution of normal and abnormal instances in wind turbine data is imperative. In this research, we propose a framework for blade icing detection utilizing a multi-head attention mechanism-based transformer. Supervisory control and data acquisition (SCADA) data is collected from wind turbines on Hitra Island, Norway, with a 10-min average interval over 12 months. To address dimensionality challenges, an autoencoder-based data compression technique is employed, followed by the application of a multi-head attention transformer for icing detection. We investigate and compare the performance of two baseline deep learning methods: convolutional neural network (CNN) and Convolutional Neural Network-Long Short-Term Memory (CNN-LSTM), against our proposed transformer framework. The results demonstrate superior accuracy and F1-score by the proposed model compared to CNN and CNN-LSTM. Additionally, we delve into a recommendation engine grounded in Bayesian inference. This engine assesses the risk associated with specific control actions, estimating conditional risk for icing and non-icing events on wind turbine blades. This Bayesian recommendation engine holds promise for real-time deployment scenarios. Harsh S. Dhiman, Shruti Patil, Shivali Amit Wagle, Nisha Soni, Ketan Kotecha, Ganeshsree Selvachandran, Ajith Abraham |
Neural Comput. Appl. | 2 |
| 2024 | Deep learning approaches for lyme disease detection: leveraging progressive resizing and self-supervised learning models
Daryl Jacob Jerrish, Om Nankar, Shilpa Gite, Shruti Patil, Ketan Kotecha, Ganeshsree Selvachandran, Ajith Abraham |
Multim. Tools Appl. | 4 |
| 2024 | An audio-based anger detection algorithm using a hybrid artificial neural network and fuzzy logic model
Arihant Surana, Manish Rathod, Shilpa Gite, Shruti Patil, Ketan Kotecha, Ganeshsree Selvachandran, Shio Gai Quek, Ajith Abraham |
Multim. Tools Appl. | 4 |
| 2024 | Understanding the Performance of AI Algorithms in Text-Based Emotion Detection for Conversational AgentsabstractCurrent industry trends demand automation in every aspect, where machines could replace humans. Recent advancements in conversational agents have grabbed a lot of attention from industries, markets, and businesses. Building conversational agents that exhibit human communication characteristics is a need in today's marketplace. Thus, by accumulating emotions, we can build emotionally aware conversational agents. Emotion detection in text-based dialogues has turned into a pivotal component of conversational agents, enhancing their ability to understand and respond to users’ emotional states. This article extensively compares various artificial intelligence techniques adapted to text-based emotion detection for conversational agents. The study covers a wide range of methods, from machine learning models to cutting-edge pre-trained models and deep learning models. We evaluate the performance of these techniques on the benchmark unbalanced Topical-Chat and balanced Empathetic Dialogue datasets. This article offers an overview of the practical implications of emotion detection techniques in conversational systems and their impact on user response. The outcomes of this work contribute to the ongoing development of empathetic conversational agents, emphasizing natural human-machine interactions. Sheetal Kusal, Shruti Patil, Jyoti Choudrie, Ketan Kotecha |
ACM Trans. Asian Low Resour. Lang. Inf. Process. | 2 |
| 2023 | Multi-fault diagnosis of Industrial Rotating Machines using Data-driven approach : A review of two decades of research
Shreyas Gawde, Shruti Patil, Pooja Kamat, Ketan Kotecha, Ajith Abraham |
Eng. Appl. Artif. Intell. | 2 |
| 2016 | MASC: Ultra-low energy multiple-access single-charge TCAM for approximate computing
Mohsen Imani, Shruti Patil, Tajana Rosing |
DATE | 2 |
| 2016 | DCC: Double Capacity Cache Architecture for Narrow-Width ValuesabstractModern caches are designed to hold 64-bits wide data, however a proportion of data in the caches continues to be narrow width. In this paper, we propose a new cache architecture which increases the effective cache capacity up to 2X for the systems with narrow-width values, while also improving its power efficiency, bandwidth, and reliability. The proposed double capacity cache (DCC) architecture uses a fast and efficient peripheral circuitry to store two narrow-width values in a single wordline. In order to minimize the latency overhead in workloads without narrow-width data, the flag bits are added to tag store. The proposed DCC architecture decreases cache miss-rate by 50%, which results in 27% performance improvement and 30% higher dynamic energy efficiency. To improve reliability, DCC modifies the data distribution on individual bits, which results in 20% and 25% average static-noise margin (SNM) improvement in L1 and L2 caches respectively. Mohsen Imani, Shruti Patil, Tajana Rosing |
ACM Great Lakes Symposium on VLSI | 2 |
| 2015 | Compiler Management of Communication and Parallelism for Quantum ComputationabstractQuantum computing (QC) offers huge promise to accelerate a range of computationally intensive benchmarks. Quantum computing is limited, however, by the challenges of decoherence: i.e., a quantum state can only be maintained for short windows of time before it decoheres. While quantum error correction codes can protect against decoherence, fast execution time is the best defense against decoherence, so efficient architectures and effective scheduling algorithms are necessary. This paper proposes the Multi-SIMD QC architecture and then proposes and evaluates effective schedulers to map benchmark descriptions onto Multi-SIMD architectures. The Multi-SIMD model consists of a small number of SIMD regions, each of which may support operations on up to thousands of qubits per cycle. Jeff Heckey, Shruti Patil, Ali Javadi-Abhari, Adam Holmes, Daniel Kudrow, Kenneth R. Brown, Diana Franklin, Fred Chong, Margaret Martonosi |
ASPLOS | 2 |
| 2015 | GazeTube: Gaze-Based Adaptive Video Playback for Bandwidth and Power OptimizationsabstractWith the popularity of mobile devices for personal entertainment, video streaming over mobile networks has seen a dramatic increase. We observe that users are often interested in just the supporting audio within the videos rather than the visual content, for example, when users play videos to listen to music. New mobile device capabilities such as gaze tracking enable easy detection of such use-cases. We propose to exploit such capabilities to selectively stream audio/video content based on user gaze. This eliminates unnecessary streaming, with twofold advantages: first, it saves precious network bandwidth for ISPs, and second, reduction in video processing decreases device power. Using an android-based gaze-aware media application, we evaluate three strategies: a maximal saving scheme that cuts off video stream at source when user gaze is directed away from the screen; a conservative scheme that reduces video resolution aimed at maintaining user experience, and a third, intermediate scheme that streams the videos at a reduced frame rate. Our evaluation shows that gaze awareness during video streaming can lead to high bandwidth savings that are linearly proportional to Gaze- OFF ratios, and up to 46% power savings on device (up to 28% power savings considering gaze tracking overheads). Shruti Patil, Tajana Rosing |
GLOBECOM | 1 |
| 2015 | CAUSE: Critical Application Usage-Aware Memory System using Non-volatile Memory for Mobile DevicesabstractMobile devices are severely limited in memory, which affects critical user-experience metrics such as application service time. Emerging non-volatile memory (NVM) technologies such as STT-RAM and PCM are ideal candidates to provide higher memory capacity with negligible energy overhead. However, existing memory management systems overlook mobile users application usage which provides crucial cues for improving user experience. In this paper, we propose CAUSE, a novel memory system based on DRAM-NVM hybrid memory architecture. CAUSE takes explicit account of the application usage patterns to distinguish data criticality and identify suitable swap candidates. We also devise NVM hardware design optimized for the access characteristics of the swapped pages. We evaluate CAUSE on a real Android smartphone and NVSim simulator using user application usage logs. Our experimental results show that the proposed technique achieves 32% faster launch time for mobile applications while reducing energy cost by 90% and 44% on average over non-optimized STT-RAM and PCM, respectively. Yeseong Kim, Mohsen Imani, Shruti Patil, Tajana Rosing |
ICCAD | 3 |
| 2015 | ScaffCC: Scalable compilation and analysis of quantum programs
Ali Javadi-Abhari, Shruti Patil, Daniel Kudrow, Jeff Heckey, Alexey Lvov, Fred Chong, Margaret Martonosi |
Parallel Comput. | 2 |
| 2012 | Weighted area technique for electromechanically enabled logic computation with cantilever-based NEMS switchesabstractNanoelectromechanical systems (NEMS) is an emerging nanoscale technology that combines mechanical and electrical effects in devices. A variety of NEMS-based devices have been proposed for integrated chip designs. Amongst them are near-ideal digital switches. The electromechanical principles that are the basis of these switches impart the capability of extremely low power switching characteristics to digital circuits. NEMS switching devices have been mostly used as simple switches to provide digital operation, however, we observe that their unique operation can be used to accomplish logic functions directly. In this paper, we propose a novel technique called `weighted area logic' to design logic circuits with NEMS-based switches. The technique takes advantage of the unique structural configurations possible with the NEMS devices to convert the digital switch from a simple ON-OFF switch to a logical switch. This transformation not only reduces the delay of complex logic units, but also decreases the power and area of the implementation further. To demonstrate this, we show the new designs of the logic functions of NAND, XOR and a three input function Y = A + B.C, and compose them into a 32-bit adder. Through simulation, we quantify the power, delay and area advantages of using the weighted area logic technique over a standard CMOS-like design technique applied to NEMS. Shruti Patil, Min-Woo Jang, Chia-Ling Chen, Zhijang Ye, Walter E. Partlo, David J. Lilja, Stephen A. Campbell, Tianhong Cui |
DATE | 1 |
| 2010 | Spintronic logic gates for spintronic data using magnetic tunnel junctionsabstractThe emerging field of spintronics is undergoing exciting developments with the advances recently seen in spintronic devices, such as magnetic tunnel junctions (MTJs). While they make excellent memory devices, recently they have also been used to accomplish logic functions. The properties of MTJs are greatly different from those of electronic devices like CMOS semiconductors. This makes it challenging to design circuits that can efficiently leverage the spintronic capabilities. The current approaches to achieving logic functionality with MTJs include designing an integrated CMOS and MTJ circuit, where CMOS devices are used for implementing the required intermediate read and write circuitry. The problem with this approach is that such intermediate circuitry adds overheads of area, delay and power consumption to the logic circuit. In this paper, we present a circuit to accomplish logic operations using MTJs on data that is stored in other MTJs, without an intermediate electronic circuitry. This thus reduces the performance overheads of the spintronic circuit while also simplifying fabrication. With this circuit, we discuss the notion of performing logic operations with a non-volatile memory device and compare it with the traditional method of computation with separate logic and memory units. We find that the MTJ-based logic unit has the potential to offer a higher energy-delay efficiency than that of a CMOS-based logic operation on data stored in a separate memory module. Shruti Patil, Andrew Lyle, Jonathan D. Harms, David J. Lilja, Jianping Wang 0006 |
ICCD | 1 |
| 2008 | Maximizing Resource Utilization by Slicing of Superscalar ArchitectureabstractSuperscalar architectural techniques increase instruction throughput by increasing resources and using complex control units that perform various functions to minimize stalls and to ensure a continuous feed of instructions to the execution units. This work proposes a dynamic scheme to increase efficiency of execution (throughput) by a methodology called block slicing. This takes advantage of instruction level parallelism (ILP) available in programs without increasing the number of execution units. Implementation of this concept in a wide, superscalar pipelined architecture introduces nominal additional hardware and delay, while offering power and area advantages. We present the design of the hardware required for the implementation of the proposed scheme and evaluate it for the metrics of speed-up, throughput and efficiency. Shruti Patil, Venkatesan Muthukumar |
DSD | 1 |
| 2005 | HAUNT-24: 24-bit Hierarchical, Application-Confined Unique Naming TechniqueabstractThe advent of tiny, inexpensive, low-power, autonomously functioning wireless sensors, has paved a way for high quality research, by posing unique challenges to researchers. Energy, cost and size of such sensors limit their communication and computation capabilities and thus robust and highly energy efficient algorithms need to be incorporated at every layer of the network model, along with an efficient network aware addressing scheme. This paper proposes a 24-bit hierarchical, application-confined unique naming technique (HAUNT-24), which ensures mutual distinctiveness of addresses within an application, with the primary focus on in-network data aggregation. Various issues relating to the proposed addressing scheme are analyzed and its future scope is discussed. The simple aggregate queries such as MIN/MAX and AVG are applied over the proposed HAUNT-24 addressed network and it's shown how it helps in achieving in-network data aggregation. Ashwini Raina, Shruti Patil, Venkatesan Muthukumar, Ajith Abraham |
ISDA | 2 |