The design and experimental evaluation of a clocked adiabatic logic (GAL) is described in this paper. CAL is a dual-rail logic that operates from a single-phase AC power-clock supply. This new low-energy logic makes it possible to integrate all power control circuitry on the chip, resulting in better system efficiency, lower cost, and simpler power distribution. CAL can also be operated from a DC power supply in a nonenergy-recovery mode compatible with standard CMOS logic. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip switching transistor and a small external inductor between the chip and a low-voltage DC supply. Circuit operation and performance are evaluated using a chain of inverters realized in a 1.2 /spl mu/m CMOS technology. Experimental results show that energy savings are achieved at clock frequencies up to about 40 MHz as compared to the nonadiabatic mode. Since CAL can operate both in adiabatic and nonadiabatic modes, power management strategies may be based upon switching between modes when necessary.

In this paper we describe the design and experimental evaluation of a clocked CMOS adiabatic logic (CAL). CAL is a dual-rail logic that operates from a single-phase AC power-clock supply in the 'adiabatic' mode, or from a DC power supply in the 'non-adiabatic' mode. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip switching transistor and a small external inductor between the chip and a low-voltage DC supply. Circuit operation and performance are evaluated using a chain of inverters realized in 1.2 /spl mu/m technology. Experimental results show energy savings in the adiabatic mode versus the non-adiabatic mode at clock frequencies up to about 40 MHz.

The accuracy and speed characteristics of implementations of several line integration models required for Radon (1917) transform (used for computed tomography image reconstruction) and backprojection computations are described and compared. The fixed-point number system used is evaluated by error comparisons to identical floating-point calculations. An expandable multiprocessor architecture for high-speed computation that has been realized as a prototype using commercially available digital signal processor (DSP) chips as the basic processing elements is described. The simulated performances of two popular DSP chips for this application are discussed and compared. Performance characteristics of the complete prototype hardware system are presented. The computational speed of a four-chip system is measured to be more than 190 times better than that of a Sun 3/160 with a math coprocessor. The architecture and prototype organization are not dependent on the DSP chip chosen, and substitution of the most up-to-date DSP chips can yield even better speed performance.>

A special-purpose VLSI array is proposed for performing the computations of the Jacobian, inverse Jacobian, direct kinematics, and numerical integration for the implementation of a joint-space position and velocity command generator for a real-time robot. This integrated approach enhances computational efficiency by reducing the duplicate calculations of these functions and maximizing the parallel/pipelining processing. The array is connected in a systolic manner to form a 6*7 array using 42 basic processing elements (PEs); 6 'circular' PEs, 30 'square' PEs, and 6 'triangular' PEs. A 'square' PE test chip has been designed and fabricated. The test results for this chip show that the array should be able to operate at a step time of 150 ns. For a six-link manipulator with rotary joints, it takes 156 steps, i.e., 23.4 mu s, to complete all the computations in one sampling period.>

A unified Radon-transform/back-projection IC that is capable of performing the forward Radon transform and back-projection computations in a multiprocessor array architecture is being designed in a CMOS technology. The architecture of the IC and related design considerations are presented. This chip would make possible high-quality image reconstruction to 12-b resolution at video rates.>

A high-speed Radon transform computer (RTC) has been designed and simulated that operates on the principles of the parallel projection pipeline engine (PPPE) processor suggested by J.L.C. Sanz, et al. (1988). The computer consists of an array of identical processing elements with fast communication links to each of its neighbors and uses forward- and back-projection formulas tests linear interpolation. Simulation and experimental timing tests have been performed on both a systolic array of 64 transputer processors and on arrays of commercial DSP (digital signal processor) chips. A custom VLSI implementation is currently under design which is expected to perform forward and inverse transforms of 512 by 512 images at or near video rates.>

A unified discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) architecture suitable for VLSI implementation is presented. A single VLSI NMOS chip design and layout for realizing this architecture is described. Algorithm simulations and experimental performance of integrated test subcircuits indicate that this chip would be capable of real-time processing of 10-MHz video signals. It is considered that circuits of this type could be very useful in real-time image data compression.>

The use of quaternary logic input and output signals for delivering information on and off chip could reduce the number of required package pins or increase the amount of information conveyed on a fixed number of package pins. In this correspondence, we discuss the performance of prototype CMOS binary-to-quaternary encoder and quaternary-to-binary decoder test circuits that have been realized on a gate array IC chip.

A unified overview of linear and nonlinear system response change induced by multiparameter or state change is presented via an investigation of system equations transformed to a parameter based representation. General matrix modification formulas, applicable to analog and digital systems, are developed for both small and large change response sensitivities. Numerous previous response change results are examined and shown to be encompassed by the general approach taken here. Detailed analysis of numerical algorithms clearly demonstrates their relative cost efficiency for a large variety of applications. Exact efficiency crossover points are identified for both recursive and nonrecursive algorithms. Applications utilizing the parameter-based response change formulation are developed in several areas. They include pole assignment, feedback compensation, system augmentation and linkage, switched capacitor network analysis, nonlinear circuit analysis, and effective medium response of random variable systems.

It is well known that multiple valued logic can theoretically provide a greater logical packing density than binary logic. In this correspondence, a useful quaternary logic arithmetic circuit is discussed in its combinational and synchronous sequential forms. The results of applying this circuit in proposed implementations of digital parallel counters are then compared to all-binary designs. A significant savings in integrated devices and thus increased packing density could be obtained in each case.

Parallel counters are multiple input circuits that count the number of their inputs that are in a given state. In this correspondence, the implementation of pipelined binary parallel counters with networks of latched quaternary threshold logic full adders is described and compared with the implementation using networks of latched binary full adders. Since each signal variable in quaternary logic may assume four logical states, twice the informational content of a binary variable, an over 50 percent savings in the total number of intermediate signal variables required to implement the parallel counter results. With the new quaternary logic circuits we will employ, over 40 percent fewer transistors and resistors are necessary for the implementation of pipelined binary parallel counters. The combination of these two factors could provide significantly reduced die areas for integrated pipelined parallel counters.

A high data-rate digital output correlator integrated circuit design which uses new synchronous sequential quaternary threshold logic gates is proposed and compared to the all-binary equivalent realization of this function. Substantial integrated circuit device count and die area savings are projected for the multiple valued logic realization.

Correlation techniques are widely used in analog and digital signal processing; e.g. in optiman receiver design. In this paper, a new digital output correlator circuit design is proposed. The correlation results are presented as a binary count of the number of bits in agreement between 31-bit reference and input sequences. Correlation results could be presented at data rates up to about 50MHz. The proposed new circuit could be implemented in a high speed bipolar transistor technology as a monolithic large-scale-integrated circuit with a power dissipation of about .5 watts. A novel pipelined 31-bit digital summing circuit will be presented that employs new multivalued, multithresholded latching and counting circuits in the formation of its binary-coded output. Comparisons with an all-binary digital correlator circuit are made.

Parallel counters are multiple-input circuits that count the number of their inputs that are in a given state. They are useful in implementing parallel multipliers, digital summers, digital correlators, and in other digital signal processing capacities. In this paper, the implementation of parallel counters with four-valued threshold logic is described and these implementations are compared to their binary full adder network counter equivalents. This logic form was selected because of the increasing importance of implementing state-of-the-art digital signal processing systems in large-scale-integrated (LSI) circuit form. LSI circuit designs are, in general, limited by the number of metal signal and power lines that must be placed upon the chip's surface, not by the number of active and passive devices used. Since each signal variable in four-valued logic may assume four logic states, twice the information carrying capacity as in binary logic, an over 50-percent savings in the total number of signal variables required to implement the parallel counter results. Also, with the circuits we describe here, approximately 50 percent fewer transistors and resistors are necessary for the implementation of four-valued logic parallel counters. These savings are attainable with a modest tradeoff in speed and power.

Parallel counters are multiple input circuits that count the number of their inputs that are in a given state. In this paper, the implementation of parallel counters with four-valued threshold logic is described and these implementation are compared to their binary full adder network counter equivalents. Since each signal variable in four-valued logic may assume four logic states, twice the information carrying capacity as in binary logic, an over fifty percent savings in the total number of signal variables required to implement the parallel counter results. With the circuits we describe here, fifty percent fewer transistors and resistors are necessary for the implementation of four-valued logic parallel counters.