Abstract – Timing verification ascertains whether timing checks on components in a circuit are satisfied given component delay models. This paper addresses timing verification of microprocessor-based designs for which previous approaches are shown to be inadequate. It introduces the concept of sequential path tracing – tracing paths through both space and time – that forms the basis of the mtv tool. mtv has the following novel features: unlike previous approaches, it considers sequential behavior together with timing and handles sequential sensitizability and multi-cycle paths automatically; it does not require a predefined clock schedule and can handle circuits with conditional or gated clocks, multiple unrelated clocks, asynchronous set/reset, and power-up initialization; it generates symbolic constraints between timing attributes of components that can be efficiently re-used for small circuit changes or by a synthesis/optimization tool; symbolic constraints also enable common ambiguity removal. Experimental results demonstrate that mtv takes only a few CPU minutes to generate symbolic constraints for each of several microprocessor-based designs. I.

A hierarchical select-and-interconnect methodology for system-level design is described. It extends the flexibility of previous approaches by allowing dynamic subproblem ordering, which is essential for this domain. The design model of M1, a knowledge-based system that implements this approach for small computer systems, is presented. M1's design space covers five microprocessor families, and it has generated hundreds of designs, three of which were built. A set of experiments showing that M1 can be used successfully to design in this complex domain and provides a substantial increase in designer productivity is described.>

Design for dependability has long been an important issue for computer systems. While several dependability analysis tools have been produced, no effort has been made to automate the design for dependability. This paper describes ASSURE, an automated design for dependability advisor, which is part of the MICON system for rapid prototyping of small computer systems. A design for dependability methodology and a formal interface between synthesis and dependability analysis are presented. ASSURE's operation includes dependability analysis, evaluation of dependability enhancement techniques using predictive estimation, and selection of a technique. Different kinds of knowledge used in designing for dependability are identified, including an algorithmic approach for dependability analysis and a knowledge-based approach for suggesting dependability enhancement techniques. Examples of designs produced using ASSURE as a dependability advisor are provided and show an order of magnitude dependability improvement.

The MICON system is an integrated collection of programs which automatically synthesizes small computer systems from high level specifications. The system addresses multiple levels of design, from logical through physical, providing a rapid prototyping capability. Two programs form MICON's nucleus: a knowledge-based synthesis tool called M1; and, an automated knowledge acquisition tool named CGEN which is used to teach M1 how to design. Other tools in the MICON system are an integrated database and associated data management tools. The system is fully functional, having been used to generate designs that have been fabricated. This paper describes the architecture and operation of the MICON system.