This paper describes the efforts made and the results of creating an Architecture Validation Suite for the PowerPC architecture.Although many functional test suites are available for multiple architectures, little has been published on how these suites are developed and how their quality should be measured.This work provides some insights for approaching the difficult problem of building a high quality functional test suite for a given architecture.By defining a set of generic coverage models that combine program-based, specification-based, and sequential bug-driven models, it establishes the groundwork for the development of architecture validation suites for any architecture.

Even though the importance of microprocessor design verification is widely acknowledged, no rigorous methodology is being commonly followed for its realization. This paper attempts to delineate such a methodology, and shows how it is promoted by Genesys, an automatic pseudo-random test-program generator. The methodology relies on a verification plan which induces smart sets of tests that carry out the verification tasks. The paper reports on an application of this methodology, using Genesys, to verify an x86 design and describes, in particular, how this methodology could have helped to avoid known escape bugs, such as the recent two infamous Pentium Floating Point bugs.

Test-program generators play a key role in hardware functional verification of large scale processors. However, in the DSP domain, the usage of full-blown test-program generators is much less popular, mainly due to the limited resources (time and money) available when developing such systems. This paper describes a work-model for the fast, low cost construction of a test-program generator for DSPs. The core technology uses Genesys, a known test program generator that, until now, has been used for the verification of large scale processor families, such as PowerPC and x86. We developed the model while using Genesys for verification of the IBM C54XDSP, a fixed-point DSP. The case study shows that it is possible to build a full test-program generator in a very short time and thus achieve better verification coverage in spite of the shorter development time.

A new methodology and test program generator have been used for the functional verification of six IBM PowerPC processors. The generator contains a formal model of the PowerPC architecture and a heuristic data-base of testing expertise. It has been used on daily basis for two years by about a hundred designers and testing engineers in four IBM sites. The new methodology reduced significantly the functional verification period and time to market of the PowerPC processors. Despite the complexity of the PowerPC architecture, the three processors verified so far had fully functional first silicon. 1 Introduction A new methodology and tool for functional test program generation has been used for several IBM PowerPC processors. The functional verification period and the processors time to market were reduced. Only one fifth of the simulation cycles needed to verify a RISC System/6000 processor with a previous generator was needed with the new methodology for a PowerPC processor. The new g...