A prototype multiprocessor system using board-to-board free-space optical interconnects distributed over the processor boards is constructed for the first time. The system consists of 64 processing units interconnected in a three-dimensional (3D) mesh network with the help of bi-directional free-space optical interconnects. Theoretical analysis of signal delay and wiring congestion characteristics in the 3-D mesh network using free-space optical interconnects concludes that the network is superior to that using a conventional backplane interconnects. In the prototype system, signal transmission of all 96 free-space optical interconnects is stable even after repeated extraction and insertion of the processor boards, and system operation without error for 100 h is performed. The system is also shown to be easy to extend to a larger and more flexible system.>

Challenges of next-generation transmission technologies are summarized in the context of creating future terabit-per-second networks. The technologies will be realized through both the separate and combined evolution of inherent lightwave capabilities along with time-, wavelength-, and space-domain optical processing techniques. Optical signal processing techniques in the tens of gigabit per second range for future high-speed transmission systems and broadband networks are reviewed.>

Parallel-processing computer systems using reconfigurable board-to-board free-space optical interconnections, called COSINE-1 and -2, are presented. In COSINE-1, 36 transputer-accommodated boards are connected by optical links comprised of collimated optical beams and optical fibers. The 144*144 crossbar interconnections are manually rearranged by operating beam couplers which couple the fiber ends to the optical beams. The system was tested for a computer graphic machine, and no degradation of performance was observed in spite of mechanical tremors. COSINE-2 uses an optical Benes switch which can electrically control the interconnection network topology. Since the interconnection state is electrically changed during the system operation, the processor can be used more efficiently. A 16-channel prototype optical switch was constructed and tested.>

A novel learning method is proposed, which is based on hardware and applicable to analog neural networks. All the network parameters (weights and thresholds) are oscillated slightly with different frequencies, and the spectra detected in the error signal are fed back to the neural network, where the network parameters are changed by a value proportional to the coherent detection signal. Since all parameters are changed in parallel, and the hardware used for learning is composed of analog circuits, this method is suited to high-speed learning. Using exclusive-OR network simulations, the effects of crosstalk between parameter control signals are discussed

Artificial neural networks are applied to fiber-optic transmission. Two fiber-optic transmission techniques using neural networks are proposed. One is an optical WDM (wavelength division multiplexing) demultiplexer composed of a simple optical component and all electrical neural network. The other is a fiber-optic image-transmission technique using a multimode fiber and a neural network. In either technique, propagation modes, in an optical multimode guide, play an important role in the signal processing. Initial experimental results are presented for these techniques. The combination of optics and neural networks have, so far, produced only the concept of optical neural networks. The techniques described can be regarded as different approaches to this combination

The authors present an LSI (large-scale integrated) circuit for high-speed inverse kinematics computation. They demonstrate that inverse kinematic solutions can be described by two-dimensional vector rotations and arc tangent operations and that these operations can be efficiently computed by the coordinate rotation digital computer (CORDIC) algorithms. The chip is fabricated using 1.5- mu m CMOS gate array technology, and the design of the arithmetic unit on the chip is based on the CORDIC algorithms. Pipelining is fully used in the processor to enhance the operating ration up to 100%. The resulting compact inverse kinematics processor is composed of the above chip and a few memory chips for program and data. The processor can be used for various kinds of manipulators.>

Future subscriber loops will provide various services including broad-band video. Fiber optic technology is the key for introducing these services. The Electrical Communication Laboratories (ECL) of Nippon Telegraph and Telephone Public Corporation (NTT) have been promoting research and development on basic technology of fiber optic subscriber loops, and studying the ways to use fiber optic subscriber loops for new services. As one of the programs, a field trial of fiber optic subscriber loops was planned and conducted in the Yokosuka area from April 1980 until May 1981. This paper first describes fiber optic transmission technologies for subscriber loops. Then, the system configuration and experimental results of the Yokosuka field trial are presented.