The steeply growing performance demands for highly power- and energy-constrained processing systems such as end-nodes of the Internet-of-Things (IoT) have led to parallel near-threshold computing (NTC), joining the energy-efficiency benefits of low-voltage operation with the performance typical of parallel systems. Shared-L1-memory multiprocessor clusters are a promising architecture, delivering performance in the order of GOPS and over 100 GOPS/W of energy-efficiency. However, this level of computational efficiency can only be reached by maximizing the effective utilization of the processing elements (PEs) available in the clusters. Along with this effort, the optimization of PE-to-PE synchronization and communication is a critical factor for performance. In this article, we describe a light-weight hardware-accelerated synchronization and communication unit (SCU) for tightly-coupled clusters of processors. We detail the architecture, which enables fine-grain per-PE power management, and its integration into an eight-core cluster of RISC-V processors. To validate the effectiveness of the proposed solution, we implemented the eight-core cluster in advanced 22 nm FDX technology and evaluated performance and energy-efficiency with tunable microbenchmarks and a set of real-life applications and kernels. The proposed solution allows synchronization-free regions as small as 42 cycles, over 41× smaller than the baseline implementation based on fast test-and-set access to L1 memory when constraining the microbenchmarks to 10 percent synchronization overhead. When evaluated on the real-life DSP-applications, the proposed SCU improves performance by up to 92 and 23 percent on average and energy efficiency by up to 98 and 39 percent on average.

Parallel ultra low power computing is emerging as an enabler to meet the growing performance and energy efficiency demands in deeply embedded systems such as the end-nodes of the internet-of-things (IoT). The parallel nature of these systems however adds a significant degree of complexity as processing elements (PEs) need to communicate in various ways to organize and synchronize execution. Naive implementations of these central and non-trivial mechanisms can quickly jeopardize overall system performance and limit the achievable speedup and energy efficiency. To avoid this bottleneck, we present an event-based solution centered around a technology-independent, light-weight and scalable (up to 16 cores) synchronization and communication unit (SCU) and its integration into a shared-memory multicore cluster. Careful design and tight coupling of the SCU to the data interfaces of the cores allows to execute common synchronization procedures with a single instruction. Furthermore, we present hardware support for the common barrier and lock synchronization primitives with a barrier latency of only eleven cycles, independent of the number of involved cores. We demonstrate the efficiency of the solution based on experiments with a post-layout implementation of the multicore cluster in a 22 nm CMOS process where the SCU constitutes less than 2 % of area overhead. Our solution supports parallel sections as small as 100 or 72 cycles with a synchronization overhead of just 10 %, an improvement of up to 14× or 30× with respect to cycle count or energy, respectively, compared to a test-and-set based implementation.

Stretchable magnetic resonance (MR) receive coils show shifts in their resonance frequency when stretched. An in-field receiver measures the frequency response of a stretchable coil. The receiver and coil are designed to operate at 128 MHz for a 3T MR scanner. Based on the measured frequency response, we are able to detect the changes of the resonance frequency of the coil. We show a proportional-integral-derivative controller that tracks the changes in resonance frequency and retunes the stretchable coil. The settling time of the control loop is less than 3.8ms. The retuning system reduces the loss in signal-to-noise ratio of phantom images from 1.6 dB to 0.3 dB, when the coil is stretched by 40% and the coil is retuned to 128 MHz.

To overcome the limitations of conventional floating-point number formats, an interval arithmetic and variable-width storage format called universal number (unum) has been recently introduced [1]. This paper presents the first (to the best of our knowledge) silicon implementation measurements of an application-specific integrated circuit (ASIC) for unum floating-point arithmetic. The designed chip includes a 128-bit wide unum arithmetic unit to execute additions and subtractions, while also supporting lossless (for intermediate results) and lossy (for external data movements) compression units to exploit the memory usage reduction potential of the unum format. Our chip, fabricated in a 65 nm CMOS process, achieves a maximum clock frequency of 413 MHz at 1.2 V with an average measured power of 210uW/MHz.

EDGE-based EC-GSM-IoT is a promising candidate for the billion-device cellular IoT (cIoT), providing similar coverage and battery life as NB-IoT. The goal of 20 dB coverage extension compared to EDGE poses significant challenges for the initial network synchronization, which has to be performed well below the thermal noise floor, down to an SNR of -8.5 dB. We present a low-complexity synchronization algorithm supporting up to 50 kHz initial frequency offset, thus enabling the use of a low-cost ±25 ppm oscillator. The proposed algorithm does not only fulfill the 3GPP requirements, but surpasses them by 3 dB, enabling communication with an SNR of -11.5 dB or a maximum coupling loss of up to 170.5 dB.

We present ongoing work on a platform for mobile health and implantable telemetry devices with powerful point-of-contact processing capabilities based on our VivoSoC multi-sensor medical instrumentation SoC, a custom power management IC, and only a few additional components - allowing the realisation of sub-ccm devices. We detail the powerful yet efficient acquisition and parallel processing capabilities on the example of first applications, demonstrate system- and chip-level power management and address the application-layer considerations of a file system optimised for serial flash devices and job scheduling.

We present an integer-N all-digital frequency-locked loop (ADFLL) suitable for dynamic voltage and frequency scaling in system-on-chips targeting mW-consumption. The proposed ADFLL operates with a 32 kHz clock reference, and offers a large clock multiplication factor of 32786, resulting in a wide tuning-range from 19 kHz to 1.048 GHz at 1.2 V and to 250 MHz at 0.8 V,. It incorporates a jitter reduction technique enabling the generation of accurate low-rate clocks in ADFLLs, combining clock division and dithering based on a 1st-order digital ΣΔ-modulator. The measured clock division factor dependent reduction of the peak cycle-to-cycle (C2C) jitter was between 40% and 70% at a 200 MHz DCO clock. The lowest peak C2C jitter of 0.14% was measured at a 3.15MHz output clock derived from a 800 MHz DCO clock. A prototype in UMC 65 nm CMOS occupies 0.013 mm2of area, and at 100 MHz consumes 605 μW (scaling with 3 μW/MHz) at 1.2 V, and 205 μW (scaling with 1.2 μW/MHz) at 0.8 V.

We consider optimal channel shortener design for a reduced-state soft-output Viterbi equalizer (RS-SOVE) in single-carrier systems. To use RS-SOVE, three receiver filters need to be designed: a prefilter, a target response, and a feedback filter. The collection of these three filters are commonly referred to as the “channel shortener.” Conventionally, the channel shortener is designed to transform an intersymbol interference (ISI) channel into an equivalent minimum-phase equivalent form. In this paper, we design the channel shortener to maximize a mutual information lower bound based on a mismatched detection model. By taking the decision-feedback quality in the RS-SOVE into consideration, the prefilter and feedback filter are found in closed forms, while the target response is optimized via a gradient-ascending approach with the gradient explicitly derived. The information theoretical properties of the proposed channel shortener are analyzed. Moreover, we show through numerical results that the proposed channel shortener design achieves superior detection performance compared with previous channel shortener designs at medium and high code rates.

The second generation (2G) cellular networks are the current workhorse for machine-to-machine (M2M) communications. Diversity in 2G devices can be present both in form of multiple receive branches and blind repetitions. In presence of diversity, intersymbol interference (ISI) equalization and co-channel interference (CCI) suppression are usually very complex. In this paper, we consider the improvements for 2G devices with receive diversity. We derive a low-complexity receiver based on a channel shortening filter, which allows to sum up all diversity branches to a single stream after filtering while keeping the full diversity gain. The summed up stream is subsequently processed by a single stream Max-log-MAP (MLM) equalizer. The channel shortening filter is designed to maximize the mutual information lower bound (MILB) with the Ungerboeck detection model. Its filter coefficients can be obtained mainly by means of discrete-Fourier transforms (DFTs). Compared with the state-of-art homomorphic (HOM) filtering based channel shortener which cooperates with a delayed-decision feedback MLM (DDF-MLM) equalizer, the proposed MILB channel shortener has superior performance. Moreover, the equalization complexity, in terms of real-valued multiplications, is decreased by a factor that equals the number of diversity branches.

This paper presents a fast-response low-dropout (LDO) regulator using a current feedback loop to realize an adaptive biasing error amplifier. With the proposed current feedback loop, the LDO regulator achieves 34dB higher loop gain, 46% faster transient response, and about 12dB higher power supply rejection above 1MHz than the one with fixed biasing. The adaptively-biased LDO regulator is compensated by a simple Miller compensation using adaptive nulling resistor (SMCANR). The proposed compensation network can realize robust frequency compensation and reduce voltage spikes during load transients. An expanded stability analysis using the Routh-Hurwitz criterion gives designers additional freedom for a stable design. Designed in a 0.13μm CMOS technology for a minimum dropout voltage of 200mV, the LDO regulator supplies 1.2V at 98.2% current efficiency and 10mA load current.

In this paper, we present a novel signal processing unit built upon the theory of factor graphs, which is able to address a wide range of signal processing algorithms. More specifically, the demonstrated factor graph processor (FGP) is tailored to Gaussian message passing algorithms. We show how to use a highly configurable systolic array to solve the message update equations of nodes in a factor graph efficiently. A proper instruction set and compilation procedure is presented. In a recursive least squares channel estimation example we show that the FGP can compute a message update faster than a state-of-the-art DSP. The results demonstrate the usabilty of the FGP architecture as a flexible HW accelerator for signal-processing and communication systems.

Modern wireless communication systems require efficient channel equalizer implementations. This paper explores the design space of reduced-state sequence estimation (RSSE). We show how the concept of pre-computation can be applied to greatly reduce computational complexity, such that efficient RSSE architectures can be derived. As a proof of concept, an RSSE was implemented in dedicated hardware, that achieves a 1.6 times higher hardware efficiency when compared to prior art.

Trellis-based channel equalization for GSM/EDGE with 8PSK modulation requires pre-filtering to achieve high performance at acceptable complexity. Since corresponding implementation complexity grows with modulation order, the introduction of 16/32QAM in the latest 2G standard Evolved EDGE requires new solutions to preserve the low-cost attribute of EDGE-enabled devices. This paper describes a novel efficient pre-filter algorithm based on homomorphic filtering. The corresponding hardware implementation in 130 nm CMOS achieves a 5× improvement of area-timing (AT-)product when compared to prior art.

This paper presents a VLSI implementation of an MMSE successive interference cancellation multiuser detector (SIC-MUD) for the downlink of a TD-SCDMA system.Computation in the frequency domain, group-wise interference cancellation, and pre-computation of filter coefficients enable an efficient architecture suitable for mobile handsets.Our implementation in 0.13µm CMOS technology proves that the SIC-MUD is a viable solution for the TD-SCDMA downlink, providing a notable performance gain at a moderate increase in complexity compared to linear equalizers.

Recognizing the importance of interfacing a variety of sensors and networking such sensors around the body area and by cellular services, a Swiss project within the Nano-Tera.ch Initiative is dedicated to developing a platform of circuit technologies for medical data acquisition and communication.

This paper addresses complexity issues at algorithmic and architectural level of digital baseband receiver ASIC design for GSM/GPRS/EDGE, in order to reduce power and die area as desired for cellular applications. A 2.5G multi-mode architecture is implemented in 0.13 μm CMOS technology occupying 1.0 mm2and dissipating only 1.3 mW in fastest EDGE data transmission mode.

A 4GHz integer-N frequency synthesizer is realized in a 0.13μm CMOS technology. It has a 400kHz reference frequency and 40kHz loop bandwidth such that 2GHz quadrature LO signals can be generated after a divide-by-two, with channel raster of 200kHz. The measured in-band phase noise is -74dBc/Hz @4kHz offset. A self-regulated charge pump is proposed to improve matching as well as charge sharing. Reference spurs are thereby kept below -55dBc over the VCO tuning voltage from rail to rail. The requirements for UMTS transceiver have been fulfilled with an overall power consumption of 9.5mW, which is the lowest reported to date. Core area of the chip is as small as 0.2mm2

An optimal design procedure to achieve minimum power consumption for a given technology and gain bandwidth is presented. Regulated cascode gain enhancement is used to ensure sufficient DC-gain at minimum gate length transistors. To validate the approach five folded cascode OTA's have been implemented, spanning a bias range of 1µA - 10mA, with measured unity-gain bandwidths within 20% of the designed value. For 17 mW at 3 V, a 0.5 µm CMOS OTA achieves 630 MHz with 51° phase margin. The method has been applied in the design of a 3rd order ΔΣ modulator for GSM receivers. The modulator consumes 2.8 mW at 3 V and has a dynamic range of 86 dB for a 100 kHz input signal bandwidth.

The current consumption of crystal oscillators is usually determined by the steady-state amplitude requirement, rather than the minimum transconductance for oscillation to exist, In a bipolar implementation transconductance is proportional to current, so that current consumption scales with frequency and load capacitance in the same way as transconductance. In a complementary metal-oxide-semiconductor (CMOS) implementation, current scales as the square of transconductance. It is therefore important to distinguish current from transconductance in power estimation for high frequency oscillators. Analytical expressions relating current to steady-state amplitude are used in this paper to estimate the minimum power required for a crystal oscillator at a given frequency. A 78 MHz crystal oscillator is described, which forms part of a regulated system in a pager where the oscillation frequency is controlled digitally to sub-ppm accuracy. The oscillator can be pulled from /spl plusmn/65 ppm to the required frequency with 0.2 ppm accuracy, with a maximum current consumption of 197 /spl mu/A. The circuit has been fabricated in a 1-/spl mu/m CMOS technology. The measured phase noise is -113 dBc/Hz at 300 Hz offset.

A 78 MHz crystal oscillator consuming 200 /spl mu/A at 1.7 V supply is described. The oscillator is part of a regulated system in a wireless device where the oscillation frequency is controlled digitally. This digital trimming of oscillation frequency is realized by binary capacitor banks of 10-bit resolution. The oscillator can be pulled from /spl plusmn/35 ppm to the required frequency with 0.3 ppm accuracy. The circuit has been fabricated in a 1 /spl mu/m CMOS technology. The measured phase noise is -100 dBc at 100 Hz offset.

A fast D-FF circuit is described which is free of the glitch problem which exists in similar circuits published recently. The glitch removal described here does not compromise the maximum achievable clock speed, which is measured at 1.54 GHz for a divide by 16 circuit and 1.39 GHz for a dual modulus prescaler.>

This paper presents a straightforward linear model applicable to two-level sigma-delta (/spl Sigma//spl Delta/) modulators of any order. In this model, the gain of the quantiser is determined from an observation that the modulator's total output power is constant. Comparisons to non-linear simulations and measurements show this model to be superior to the commonly cited unity gain quantiser model.>