Demo Data from VLDB 2026 / reviewers in the wild / expert
Nhon T. Quach
dblp:38/6333
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 2004
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-authorTheory of computation · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 93% Processor architecture and microarchitecture · 7% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › digital circuit design › arithmetic circuit design
adder design |
0.0 | 1 | 1992 | High-Speed Addition in CMOS · IEEE Trans. Computers 1992 |
Integrated circuit design › digital circuit design › arithmetic circuit design › adder design
carry-lookahead adder |
0.0 | 1 | 1992 | High-Speed Addition in CMOS · IEEE Trans. Computers 1992 |
Integrated circuit design › semiconductor device fabrication
CMOS technology |
0.0 | 1 | 1992 | High-Speed Addition in CMOS · IEEE Trans. Computers 1992 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1992 | High-Speed Addition in CMOS · IEEE Trans. Computers 1992 |
Processor architecture and microarchitecture › arithmetic unit
arithmetic logic unit |
0.0 | 1 | 1992 | High-Speed Addition in CMOS · IEEE Trans. Computers 1992 |
Methods — techniques the papers use, named apart from their topics
static CMOS · 0.0ling-type adder · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2004 | Systematic IEEE rounding method for high-speed floating-point multipliersabstractFor performance reasons, many high-speed floating-point multipliers today precompute multiple significand values (SVs) in advance. The final normalization and rounding steps are then performed by selecting the appropriate SV. While having speed advantages, this integrated rounding method complicates the development of the rounding logic significantly, hence, requiring a systematic rounding method. The systematic rounding method, presented in this paper, has three steps: 1) constructing a rounding table; 2) developing a prediction scheme; and 3) performing rounding digits selection (RDS). The rounding table lists all possible SVs that need to be precomputed. Prediction reduces the number of these SVs for efficient hardware implementation while RDS reduces the complexity of the rounding logic. Both prediction and RDS depend on the specifics of the hardware implementation. Two hardware implementations are described. The first one is modeled after that reported by Santoro et al. and the second improved one supports all IEEE rounding modes. Besides allowing systematic hardware optimization, this rounding method has the added advantage that verification and generalization are straightforward. Nhon T. Quach, Naofumi Takagi, Michael J. Flynn |
IEEE Trans. Very Large Scale Integr. Syst. | 1 |
| 1995 | The SNAP Project: Towards Sub-Nanosecond ArithmeticabstractSNAP-the Stanford subnanosecond arithmetic processor-is an interdisciplinary effort to develop theory, tools, and technology for realizing an arithmetic processor with execution rates under 1 ns. Specific improvements in clocking methods, floating-point addition algorithms, floating-point multiplication algorithms, division and higher-level function algorithms, design tools, and packaging technology were studied. These improvements have been demonstrated in the implementation of several VLSI designs.> Michael J. Flynn, Kevin J. Nowka, Gary Bewick, Eric M. Schwarz, Nhon T. Quach |
IEEE Symposium on Computer Arithmetic | 5 |
| 1992 | High-Speed Addition in CMOSabstractA fully static complementary metal-oxide semiconductor (CMOS) implementation of a Ling-type 32-bit adder is described. The implementation saves up to one gate delay and always reduces the number of serial transistors in the worst-case critical path over the conventional carry look-ahead (CLA) approach with a negligible increaser in hardware.> Nhon T. Quach, Michael J. Flynn |
IEEE Trans. Computers | 1 |