Breast ultrasound tumor segmentation is critical for early diagnosis and treatment planning. However, due to the high similarity between tumors and background tissue in ultrasound images, achieving accurate segmentation poses significant challenges. To address this, we propose a Masked Separable Attention Network (MSA-Net), a segmentation model based on an encoder-decoder architecture. The model employs PVTv2 as the feature extraction backbone encoder and introduces our designed Masked Separable Attention (MSA) module. The core innovation of the MSA module lies in separating the multi-head self-attention mechanism into three function-specific subgroups: the foreground attention group focuses on the tumor region, the background attention group focuses on the surrounding tissue, and the global attention group captures the overall image information. This structured attention mechanism aims to more effectively model the contextual relationships between the tumor region, background region, and the entire image, thereby significantly enhancing the model's ability to distinguish between tumors and background tissue. Extensive experiments demonstrate that our MSA-Net achieves competitive performance compared to state-of-the-art breast tumor segmentation methods. Ablation studies further confirm the effectiveness and complementary of each component in our MSA-Net. The code is available at https://github.com/chenwang1701/MSA-Net.

This paper presents a compact 11-bit source driver for mobile OLED displays to achieve high uniformity. The proposed driver consists of a 5-bit high voltage resistor string digital to analog converter (HV-RDAC), a 6-bit low voltage resistor string digital to analog converter (LV-RDAC), and a switch capacitor adder (SC-Adder). This one-stage 11-bit hybrid DAC only needs 544 transistors, resulting in a true 10-bit display effect after gamma correction. The area of the proposed 11-bit source driver is only 36.8% of that of the conventional 8-bit high-voltage source driver. Furthermore, a capacitor-exchange method is introduced to address the non-uniformities among channels caused by capacitor mismatches. As a result, the maximum deviations of voltage outputs (DVOs) between 60 channels are 3 mV (without the capacitor-exchange method) and 1.5 mV (with the capacitor-exchange method). The worst differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.63 and 0.62 LSB respectively.

This paper demonstrates a highly reliable active pixel sensor (APS) based on dual-gate (DG) thin-film transistors (TFTs) for high-frame-rate dynamic X-ray medical imaging. By storing the threshold voltage (VT) in the auxiliary gate capacitor and amplifying the voltage signal through the primary gate electrode, the proposed APS circuit compensates for both positive and negative VTshifts of the amplifying TFT. Furthermore, using correlated double sampling by successively subsampling the same pixel without additional memory, the APS circuit eliminates low-frequency noise and DC offset, thereby effectively increasing the dynamic range and the signal-to-noise ratio. The charge-to-current gain of the proposed circuit is 4.50 μA/pC with a nonlinearity of 1.02%. Compared with the conventional 3-T pixel, the proposed APS features a decreased voltage error rate from 23.85% to 0.88% with a VTshift of ±1 V.

In-Sensor computing has emerged as a promising approach for fast, energy-efficient visual perception. This paper presents an in-sensor computing system that leverages amorphous metal oxide thin-film transistors (TFTs) for photo-sensing, computation, and control, enabling rapid and precise visual processing. The system directly computes the first layer of a neural network (NN) during exposure and supports high-resolution raw image readout once a target of interest is detected. The pixel circuit incorporates threshold voltage (VTH) compensation to ensure computational accuracy. Validated on the MNIST dataset, the system achieves 88% classification accuracy with only a 2.2% degradation under a 2V VTHshift. Post-Simulation results show that one computation frame can be finished within 500 ns, demonstrating a 20× speed enhancement over state-of-the-art silicon-based solutions.

This paper presents a highly robust -4V DC-DC converter composed of low-temperature poly-Si oxide (LTPO) TFTs. The proposed circuit significantly reduces the off-state overdrive voltage using the negative voltage bootstrapping technique, thus enhancing the circuit robustness in against VTHshifts for flexible applications. A dual-gate feedback is adopted in the loop control system for a reliable and constant output performance. The post-layout simulation results demonstrate that the steady-state voltage deviation remains below 1%, whereas the conventional design suffers from a voltage degradation of 17.1% for a VTHshift of ±3 V. Furthermore, the compact DC-DC converter achieves maximum power efficiency of 93.7% @20 μA, and 84.1% @100 μA.

Single image dehazing has been extensively studied. While convolutional neural networks (CNNs) have driven notable progress in single image dehazing, their performance remains fundamentally constrained by the limited local receptive fields of convolutional operations, which impede the capture of global structural dependencies. In contrast, generative adversarial networks (GANs) have demonstrated exceptional capabilities in image synthesis, offering global insights into structure, texture, and color. The fuzzy prior, a probabilistic knowledge acquired through adversarial training in GANs, plays a pivotal role in robust dehazing. Motivated by this, we propose the fuzzy prior guided dehazing network (FPGDN). Our framework begins with a novel module that distills the fuzzy prior by translating an edge map into a color image, simultaneously capturing global structural, local textural, and color information. Subsequently, a dehazing network is constructed, leveraging this fuzzy prior. While the fuzzy prior captures rich color and texture features, the generated images may exhibit color shifts relative to the original scene. To remedy this, a CNN network is employed to capture local nuances and refine the dehazing outcome. Extensive experiments substantiate that the proposed FPGDN achieves superior dehazing performance on a variety of real and synthetic hazy images.

This paper presents a capacitive sensing circuit for high-throughput active-matrix (AM) thin-film transistor (TFT) digital microfluidic (DMF) chips, with highly parallel operations to reduce frame time and thereby enhance chip throughput. The proposed circuit integrates a capacitance-to-frequency converter (CFC) into each DMF cell column, enabling simultaneous capacitance sensing and readout of DMF cells in the same row. Furthermore, a pipelined control scheme is devised to parallelize operations across rows, reducing frame time by over 81% compared to conventional DMF chips. Integrated with double-gate (DG) unipolar n-type amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs, the proposed circuit achieves a sensitivity of 13.06 kHz/pF and a resolution of 7.2 fF for a DMF array scale of 150 × 300.

Owing to the fast developments of economics, a lot of devices and objects have been connected and have formed the Internet of Things (IoT). Visual sensors have been applied in vehicle navigation, traffic situational awareness, and traffic safety management. However, the particles in the air degrade the imaging quality, which affects the performance of vehicle navigation, traffic situational awareness, and traffic safety management. Deep-learning-based dehazing methods were proposed to address this issue. However, these methods are trained with simulated hazy images and cannot generalize to natural haze images well. To address the domain shift problem, some methods resort to zero-shot learning or domain adaption to boost the generalization of the model on natural haze images. However, the relevance between dehazed results and clean images is ignored by zero-shot dehazing methods. Domain-adaption-based dehazing methods ignore the relationship between the dehazed results and the hazy images. To overcome these issues, a generative adversarial and self-supervised dehazing network is introduced to boost the dehazing performance on real haze images. First, generative adversarial is employed to construct the relevance between dehazed results and haze-free images, which can boost the natural appearance of dehazed results. Second, self-supervised learning is employed to construct the relevance between the dehazed results and hazy images, which can restrict the solution space of dehazing. To show the effectiveness of the proposed model, we conduct extensive experiments on real and simulated haze images. Compared with state-of-the-art methods, the proposed model achieves state-of-the-art dehazing performance.

Despite that convolutional neural networks (CNNs) have shown high-quality reconstruction for single image dehazing, recovering natural and realistic dehazed results remains a challenging problem due to semantic confusion in the hazy scene. In this article, we show that it is possible to recover textures faithfully by incorporating semantic prior into dehazing network since objects in haze-free images tend to show certain shapes, textures, and colors. We propose a semantic-aware dehazing network (SDNet) in which the semantic prior is taken as a color constraint for dehazing, benefiting the acquisition of a reasonable scene configuration. In addition, we design a densely connected block to capture global and local information for dehazing and semantic prior estimation. To eliminate the unnatural appearance of some objects, we propose to fuse the features from shallow and deep layers adaptively. Experimental results demonstrate that our proposed model performs favorably against the state-of-the-art single image dehazing approaches.

The goal of the next-generation mobile communication system is higher data-rates, lower latency, and higher energy-efficient performance, which bring about the demands for fast beam tracking in time-varying mobile communication. With the development of large-scale antenna array technology, highly directional beams can be formed with limited radio frequency chains. However, traditional exhaustive searching scheme has unacceptable overhead that leads to great challenges for applying to mobile millimeter-wave environments. Fast beam tracking scheme therefore has been recognized as a key technology in millimeter wave communication. To address this issue, this paper proposes a data-driven multi-armed beam tracking scheme to select the beamforming/combining vectors that achieve the target quality of service based on the real-time measurement, rather than the prior knowledge such as channel and user mobility information in beamforming design. To further speed up the beam tracking process, multi-armed beam is created to sample multiple spatial directions simultaneously. Simulation results show that the proposed data-driven multi-armed beam tracking method could achieve fast beam tracking performance with high resolution and reduced training overhead.

A reconfigurable cyclic shifter is a key element of a QC-LDPC decoder, which is crucial for 5G communication systems. If a traditional reconfigurable cyclic shifter can only shift one input of variable size at a time, a traditional QC-LDPC decoder can only decode one codeword at a time as well. Part of the circuitry of the traditional QC-LDPC decoder inevitably stays in idle during the decoding process if the length (or the lifting parameter) of a codeword is not the maximum, resulting in low hardware efficiency. A segmented reconfigurable cyclic shifter is proposed in this paper, which can be divided into multiple segments of different sizes. Each segment can perform a cyclic shift of an input of different sizes and of different shift values independently. Furthermore, a methodology is proposed to upgrade any state-of-the-art QC-LDPC decoder to a segmented QC-LDPC decoder, by using the proposed segmented shifter. The upgraded segmented QC-LDPC decoder is able to parallelly decode multiple codewords (or inputs) of different lengths at a time. A test chip of the proposed segmented QC-LDPC decoder with the proposed segmented reconfigurable cyclic shifter has been fabricated in a 0.18-$\mu \text{m}$CMOS technology to demonstrate the feature of parallelly decoding multiple codewords. The performance analysis shows that when the number of small codewords is increased from 0 to 100000 per second, the throughput of the traditional QC-LDPC decoder drops from 844.80 Mbps to 4.40 Mbps, while the QC-LDPC decoder with the proposed segmented shifter only slightly drops to 814.01 Mbps. By applying the segmented QC-LDPC decoder in 5G base stations, the base stations are enabled to support more low-traffic users.

The commonly used atmospheric model in image dehazing cannot hold in real cases. Although deep end-to-end networks were presented to solve this problem by disregarding the physical model, the transmission map in the atmospheric model contains significant haze density information, which cannot simply be ignored. In this article, we propose a novel hierarchical density-aware dehazing network, which consists of a the densely connected pyramid encoder, a density generator, and a Laplacian pyramid decoder. The proposed network incorporates density estimation but alleviates the constraint of the atmospheric model. The predicted haze density then guides the Laplacian pyramid decoder to generate a haze-free image in a coarse-to-fine fashion. In addition, we introduce a multiscale discriminator to preserve global and local consistency for dehazing. We conduct extensive experiments on natural and synthetic hazy images, which prove that the proposed model performs favorably against the state-of-the-art dehazing approaches.

Batch Normalization (BN) is a popular technique for training Deep Neural Networks (DNNs). BN uses scaling and shifting to normalize activations of mini-batches to accelerate convergence and improve generalization. The recently proposed Iterative Normalization (IterNorm) method improves these properties by whitening the activations iteratively using Newton’s method. However, since Newton’s method initializes the whitening matrix independently at each training step, no information is shared between consecutive steps. In this work, instead of exact computation of whitening matrix at each time step, we estimate it gradually during training in an online fashion, using our proposed Stochastic Whitening Batch Normalization (SWBN) algorithm. We show that while SWBN improves the convergence rate and generalization of DNNs, its computational overhead is less than that of IterNorm. Due to the high efficiency of the proposed method, it can be easily employed in most DNN architectures with a large number of layers. We provide comprehensive experiments and comparisons between BN, IterNorm, and SWBN layers to demonstrate the effectiveness of the proposed technique in conventional (many-shot) image classification and few-shot classification tasks.

In various wireless communication standards, such as Wi-Fi, WiMAX, and 5G standards, QC-LDPC decoders are required to decode a codeword of variable length. Part of the decoder is in idle if the length of codeword is not the maximum. A reconfigurable cyclic shifter is a key element of a QC-LDPC decoder. If the shifter can only shift one input at a time, the QC- LDPC decoder can only decode one codeword at a time as well. A segmented reconfigurable cyclic shifter is proposed in this paper to enable a QC-LDPC decoder to parallelly decode multiple codewords. The proposed shifter can be reconfigured into multiple segments of different sizes. Each segment can perform a cyclic shift of different shift values independently. Therefore, the proposed shifter can enhance the QC-LDPC decoder to decode multiple codewords parallelly by inputting another codeword (or codewords) to re-activate the idle hardware. The test chip of QC- LDPC decoder with the proposed segmented reconfigurable cyclic shifter has been fabricated in 0.18μ CMOS technology which can parallelly decode six codewords.

Thin-film transistor (TFT) not only is the backbone of display technology, but also brings in fancy applications in the area of flexible electronics. TFT-based flexible circuit design however faces various challenges, such as unipolar devices and severe nonuniformity. In this paper, a sense amplifier based on dual-gate indium-gallium-zinc oxide (IGZO) TFTs is proposed for TFT-based static random access memory (SRAM) circuits. The pull-up transistors in the proposed sense amplifier are implemented with dual-gate TFTs while the pull-down transistors are implemented with conventional bottom-gate TFTs. By tuning the top gate of the pull-up transistors to achieve a negative threshold voltage as well as employing a specialized strength- adaptive pull-up structure, the proposed sense amplifier aims to reduce the offset voltage, sensing delay, and sensing power consumption simultaneously. Compared to the state-of-the-art IGZO-based sense amplifier, the proposed sense amplifier achieves up to 66.1% lower offset voltage, 68.9% shorter sensing delay, 72% dynamic power savings, and 66.3% leakage power savings.

N×N filter operations are frequently used in various image processing algorithms in display driver circuits. The implementation of the N×N filter requires a storage element to temporarily retain N or N-1 lines of display data. The traditional approach for this temporary storage element for N×N image filter is either by using N blocks of memory to store N lines of display data with single-port six-transistor (6T) SRAM bit-cells or by using N-1 blocks of memory to store N-1 lines of display data with dual-port eight-transistor (8T) SRAM bit-cells. In this paper, a pseudo multi-port SRAM circuit is proposed for N×N filter in image processing in a display driver integrated circuit (IC). By using pre-read mechanism and word-line/column selection signal forwarding technique, the proposed approach only stores N-1 lines of display data and can use the small single-port 6T SRAM bit-cells. For a 3×3 filter application, the proposed approach reduces the overall layout area by 50.3% and 30.2% compared to the traditional dual-port 8T and single-port 6T memory implementations, respectively, in an industrial 0.18- μm CMOS technology. Furthermore, the power used to perform a 3×3 filter operation is reduced by 47% and 30.8% with the proposed approach as compared to the traditional dual-port 8T and signal-port 6T memory circuits, respectively, with slight degradation of the access speed.

An on-chip compensation system which is composed of an analog voltage adder and an 8-bit R-C digital-to-analog converter (DAC) is proposed for active matrix organic light-emitting diode (AMOLED) display drivers. The proposed analog voltage adder uses two groups of rail-to-rail input MOSFETs, which can work alternately, thereby extending the effective driving time (EDT) to 100%. The 8-bit R-C DAC is composed of a 5-bit R-DAC and a 3-bit C-DAC. The 3-bit C-DAC shares the capacitors with the analog voltage adder, reducing the layout area by 65% compared to the conventional method. This work is implemented in an industrial 0.18-μm CMOS technology. The measurement results show that the maximum INL of the system is 0.254 LSB, while the maximum DNL is 0.506 LSB. The layout area is only 9180 μm2per channel.

A compact low-voltage segmented digital to analog (D/A) converter with adjustable gamma correction coefficient is proposed for source drivers of active matrix organic light-emitting diode (AMOLED) displays. The shared resistor-string is separated into several segments. The switching networks for each segmentation could be realized using low-voltage or mediumvoltage transistors. The outputs of the segmented DACs are added up by an analog adder to obtain the final DAC value. Compared to the conventional resistor string DAC (R-DAC) with high-voltage transistors, the proposed D/A converter features the layout area reduction by 84.7%, due to the elimination of high-voltage transistors. The proposed segmented DAC is implemented in an industrial 0.25-μm CMOS technology. The measurement results show that the differential and integral nonlinearity of the proposed D/A converter are 0.21 LSB and 1.31 LSB, respectively, which are significantly lower compared to the previously published high resolution DACs. The deviation of output voltages is also reduced by up to 2.9× compared to the previously published high resolution DACs.

This paper proposes an image dehazing model built with a fully convolutional neural network (CNN), called Fully End-to-End Dehazing Network (FEED-Net). In contrast to estimate the transmission map and the atmospheric light separately as most previous deep learning methods, FEED-Net recovers the hazy-free image directly from a hazy image via a light-weight CNN. In addition, we introduce contextual information into dehazing via dilated convolution and use dense skip connection for feature fusion, which makes end-to-end dehazing possible. Experimental results show our method outperforms the state-of-the-art algorithms on both synthetic dataset and real-world images.

This paper presents a pixel-level ADC for 640×512 mid-wavelength infrared focal plane arrays. The pulse comparator for windowed signal used in the single-slope structure proposed in this work obtains lower power consumption and lower RMS noise than conventional designs. Moreover, by employing a novel low-load 3T NMOS memory structure, hardware cost can be reduced. The pixel circuit with 15μm-pitch has been designed in the 0.18um 1P6M CMOS process. Power consumption of the pixel-level ADC is 0.107μW and the charge handling capacity is 10Me-per pixel. Depending on the simulation results, an average output RMS noise of 2LSB and a maximum nonlinearity of 0.15% are demonstrated.

In this paper, we consider the problem of event prediction with multi-variate time series data consisting of heterogeneous (continuous and categorical) variables. The complex dependencies between the variables combined with asynchronicity and sparsity of the data makes the event prediction problem particularly challenging. Most state-of-art approaches address this either by designing hand-engineered features or breaking up the problem over homogeneous variates. In this work, we formulate the (rare) event prediction task as a classification problem with a novel asymmetric loss function and propose an end-to-end deep learning algorithm over symbolic representations of time-series. Symbolic representations are fed into an embedding layer and a Long Short Term Memory Neural Network (LSTM) layer which are trained to learn discriminative features. We also propose a simple sequence chopping technique to speed-up the training of LSTM for long temporal sequences. Experiments on real-world industrial datasets demonstrate the effectiveness of the proposed approach.

In this paper, we introduce a generic model to deal with the event matching problem of content-based publish/subscribe systems over structured P2P overlays. In this model, we claim that there are three methods (event-oriented, subscription-oriented and hybrid) to make all the matched pairs (event, subscription) meet in a system. By theoretically analyzing the inherent problem of both event-oriented and subscription-oriented methods, we propose PEM (Popularity-based Event Matching), a variant of hybrid method. PEM can achieve better trade-off between event processing load and subscription storage load of a system. PEM has been verified through both mathematical and simulation-based evaluation.

The Internet-based Virtual Computing Environment (iVCE) provides on-demand aggregation and autonomic collaboration mechanisms to facilitate the utilization of autonomous and dynamic Internet resources. Load balancing and fault tolerance are important issues when scheduling those transient resources. In this paper, we propose a mobility mechanism for the migration of various roles of agents in the iVCE platform. The mobility mechanism involves two parts of the iVCE platform: role container layer and event service layer. At the role container layer, a novel approach is proposed to handle the code and data mobility issue. At the event service layer, an efficient routing reconfiguration protocol is proposed based on a publish/subscribe system over DHTs to facilitate task migrations. Certain conditions must be satisfied before the migration of an agent to ensure the correctness of the whole process. Experiments are conducted to evaluate the performance of the mobility mechanism, and the experimental results show that it is suitable for implementing load balancing and fault tolerance in the iVCE.