This paper describes the early vision of bio-inspired neuromorphic system enhanced by fuzzy processing, mimicking the primitive behaviour of visual cortex. The proposed bio-inspired system exhibits the biologically plausible function of mimicking the cat's visual cortex experimentation of Hubel and Wiesel. The neuromorphic implementation of vision is inspired by the directional visual signal selectivity of cortex and the CMOS spiking neuron based on Hodgkin-Huxley formalism. The membership function is introduced to improve the early vision and the improvement is demonstrated for robust applications, based on the recognition of human head figures.

This paper describes a way of implementing programmable analog membership function of fuzzy hardware, which is compatible to neural networks based on electronically programmable conductance. The theoretical model of electronic implementation is analyzed and verified by the measurement of CMOS test device and SPICE simulation. The analog membership function circuit is based on new input signal shaping circuit and neural networks circuit for Hodgkin-Huxley dynamic based neuron. The flexibility of programming is implemented by quadratic function of MOSFET in saturation region, and the Gaussian function by multiplying synapse circuit based on MOSFET in triode region. The circuit allows various membership functions with the linearity of 0.1%. The new membership function can realize the mixed hardware of fuzzy function and biologically plausible neural networks.

This paper describes a way of implementing neural networks in biologically inspired hardware, based on electronically programmable conductance. The theoretical model of electronic implementation is analyzed and verified by the measurement of CMOS test device, SPICE and MATLAB simulation. A new analog multiplier is presented to enforce previous elements of implementing spike-based neural networks and Hodgkin-Huxley dynamic based neuron. The proposed analog multiplier is implemented by a parallel connection of two conductance-based synapse circuits, and its power consumption is 250frac14W with the simulated accuracy of 0.1%. The hardware implementation based on programmable conductance exhibits the low power consumption, biological plausibility, flexibility to various applications of asynchronous integration-and-firing, neural oscillator, and vision processing.

This paper describes a new pulse-based neural network VLSI based on the tunable linear conductance of MOSFET circuit. The controlled conductance produces the synaptic or neuron function, which are inspired by the biological plausibility and low power consumption. The synaptic computation speed is up to maximum pulse frequency. The power consumption is reduced, as active synapses only consume the power. The neuron based on the controlled conductance demonstrates the asynchronous pulse generation with a refractory period, and the behavior of integration-and-firing. The neural network VLSI is fabricated in 0.7 micron CMOS. The experimentation exhibits the behavior of linear controlled conductance, as observed in SPICE simulation.

This paper describes a new asynchronous spike based neural networks VLSI implementation, inspired by the biological plausibility and low power requirement. The voltage-controlled linear conductance produces the synaptic function of multiplication, weight programming, and summation of synaptic spike currents for the neuron. The operation speed of synaptic computation is up to 300 Mega operations with a small power consumption of 33 microwatts. The overall power consumption can be less in real applications, as individual synapse only consumes the power when there is an active neural input. The neuron is based on multiple combinations of synapses and the HSPICE simulation demonstrates the asynchronous spike behavior of integration-and-firing with a refractory period. The advantages of asynchronous operation, removal of reference clocks, and low voltage operation are exhibited compared to previous pulse-based analogue-mixed neural networks VLSI. The asynchronous spike based neural networks in 0.18/spl mu/m CMOS VLSI technology is proposed to provide the advantage of analogue-mixed neural network VLSI with small power consumption and no need for a synchronous operation.

implement Korean This paper describes a way of neural hardware implementation with the analog-digital mixed mode neural chip. The full custom neural VLSI of Universally Reconstructible Artificial Neural network (URAN) is used system. A to multi-layer perceptron with is trained successfully under the limited accuracy in computations. The network with a large frame input layer is tested to recognize spoken korean words at a forward retrieval. Multichip hardware module is suggested with eight chips or more for the extended performance and capacity.