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Shengyu He

dblp:38/8598 · DBLP profile ↗
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4ranked-venue papers
1as first author
2since 2021 · last 2023
0009-0007-4971-8231ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 first-author · 2 since 2021Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
1 paper
3D vision · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 50% Reconfigurable computing and FPGAs · 50%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Computer vision › 3D vision › depth estimation
dense depth estimation
0.412020
StereoEngine: An FPGA-Based Accelerator for Real-Time High-Quality Stereo Estimation With Binary Neural Network · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Computer vision › 3D vision › stereo vision
stereo matching
0.412020
StereoEngine: An FPGA-Based Accelerator for Real-Time High-Quality Stereo Estimation With Binary Neural Network · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Reconfigurable computing and FPGAs
FPGA accelerator
0.412020
StereoEngine: An FPGA-Based Accelerator for Real-Time High-Quality Stereo Estimation With Binary Neural Network · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Hardware accelerators and domain-specific architectures › vision accelerator
stereo vision accelerator
0.412020
StereoEngine: An FPGA-Based Accelerator for Real-Time High-Quality Stereo Estimation With Binary Neural Network · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020

Methods — techniques the papers use, named apart from their topics

pipelined hardware architecture · 0.9binary neural network · 0.9
YearPublicationVenuePosition
2023 A GPU-accelerated real-time human voice separation framework for mobile phones
Gang Chen 0023, Zhaoheng Zhou, Shengyu He, Wang Yi 0001
J. Syst. Archit.4
2021 An efficient GPU-accelerated inference engine for binary neural network on mobile phones
Shengyu He, Haitao Meng, Zhaoheng Zhou, Kai Huang 0001, Gang Chen 0023
J. Syst. Archit.1
2020 PhoneBit: Efficient GPU-Accelerated Binary Neural Network Inference Engine for Mobile Phones
abstract
Over the last years, a great success of deep neural networks (DNNs) has been witnessed in computer vision and other fields. However, performance and power constraints make it still challenging to deploy DNNs on mobile devices due to their high computational complexity. Binary neural networks (BNNs) have been demonstrated as a promising solution to achieve this goal by using bit-wise operations to replace most arithmetic operations. Currently, existing GPU-accelerated implementations of BNNs are only tailored for desktop platforms. Due to architecture differences, mere porting of such implementations to mobile devices yields suboptimal performance or is impossible in some cases. In this paper, we propose PhoneBit, a GPU-accelerated BNN inference engine for Android-based mobile devices that fully exploits the computing power of BNNs on mobile GPUs. PhoneBit provides a set of operator-level optimizations including locality-friendly data layout, bit packing with vectorization and layers integration for efficient binary convolution. We also provide a detailed implementation and parallelization optimization for PhoneBit to optimally utilize the memory bandwidth and computing power of mobile GPUs. We evaluate PhoneBit with AlexNet, YOLOv2 Tiny and VGG16 with their binary version. Our experiment results show that PhoneBit can achieve significant speedup and energy efficiency compared with state-of-the-art frameworks for mobile devices.
Gang Chen 0023, Shengyu He, Haitao Meng, Kai Huang 0001
DATE2
2020 StereoEngine: An FPGA-Based Accelerator for Real-Time High-Quality Stereo Estimation With Binary Neural Network
abstract
Stereo estimation is essential to many applications such as mobile autonomous robots, most of which ask for real-time response, high energy, and storage efficiency. Deep neural networks (DNNs) have shown to yield significant gains in improving accuracy. However, these DNN-based algorithms are challenging to be deployed on energy and resource-constrained devices due to the high computational complexities of DNNs. In this article, we present StereoEngine, a fully pipelined end-to-end stereo vision accelerator that computes accurate dense depth in a real-time and energy-efficient manner. An efficient stereo algorithm is developed and optimized for a high-quality hardware-friendly implementation, that leverages binary neural network (BNN) to learn discriminative binary descriptors to improve the disparity. The design of StereoEngine is a standalone DNN-based stereo vision system where all processing procedures are implemented on a hardware platform. The effectiveness of StereoEngine is evaluated by comprehensive experiments. Compared with software-based implementations on the highend and embedded Nvidia GPUs, StereoEngine achieves up to 3×, 13×, and 50× speedups, as well as up to 211×, 58×, and 73× energy efficiency improvement, respectively. Furthermore, StereoEngine achieves leading accuracy when compared to state-of-the-art hardware implementations on the challenging KITTI dataset.
Gang Chen 0023, Yehua Ling, Haitao Meng, Shengyu He, Kai Huang 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5