Demo Data from VLDB 2026 / reviewers in the wild / expert
Sanjali Yadav
dblp:380/0105
· DBLP profile ↗
3ranked-venue papers
2as first author
3since 2021 · last 2026
0009-0000-5611-5892ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware accelerators and domain-specific architectures · 87% Parallel and multicore computing · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures
sparse matrix multiplication accelerator |
0.9 | 1 | 2025 | Misam: Machine Learning Assisted Dataflow Selection in Accelerators for Sparse Matrix Multiplication · MICRO 2025 |
Hardware accelerators and domain-specific architectures › sparsity exploitation
sparsity-aware accelerator |
0.9 | 1 | 2025 | Bootes: Boosting the Efficiency of Sparse Accelerators Using Spectral Clustering · MICRO 2025 |
Parallel and multicore computing
task partitioning |
0.3 | 1 | 2025 | Bootes: Boosting the Efficiency of Sparse Accelerators Using Spectral Clustering · MICRO 2025 |
Methods — techniques the papers use, named apart from their topics
spectral clustering · 0.9machine learning · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Situla: Studying the Interplay of Sparse Formats and CPU/GPU LibrariesabstractThe abundance of sparse matrix formats, vendor libraries, and heterogeneous hardware architectures creates a complex optimization landscape in which performance depends on the interplay among data representation, software implementation, and hardware capabilities. To address this complexity, we present Situla, a comprehensive characterization of sparse-dense and sparse-sparse matrix multiplication across Intel Xeon CPUs, NVIDIA H100 GPUs, and many-core ARM Neoverse processors. Our systematic evaluation of CSR, CSC, BSR, and COO formats demonstrates that hardware superiority is not absolute but is instead contingent on software efficiency and matrix structure. Notably, a custom OpenMP implementation on ARM CPUs can outperform vendor-optimized libraries and achieve GPU-level performance for a significant subset of workloads. By analyzing latency, throughput, and power efficiency across diverse matrices from the SuiteSparse collection, Situla challenges conventional assumptions regarding accelerator dominance and highlights critical trade-offs between format selection, platform choice, and energy consumption. Situla’s findings can serve as a blueprint for developing sparsity-aware runtime systems capable of intelligent, dynamic workload scheduling in largescale heterogeneous environments. Amirmahdi Namjoo, Sanjali Yadav, Helya Hosseini, Bahar Asgari |
ISPASS | 2 |
| 2025 | Bootes: Boosting the Efficiency of Sparse Accelerators Using Spectral Clustering
Sanjali Yadav, Bahar Asgari |
MICRO | 1 |
| 2025 | Misam: Machine Learning Assisted Dataflow Selection in Accelerators for Sparse Matrix Multiplication
Sanjali Yadav, Amirmahdi Namjoo, Bahar Asgari |
MICRO | 1 |