Demo Data from VLDB 2026 / reviewers in the wild / expert
Lily Jiaxin Wan
dblp:380/7628
· DBLP profile ↗
4ranked-venue papers
2as first author
4since 2021 · last 2026
0000-0001-8006-0019ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 first-author · 4 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 56% Electronic design automation · 44% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization
accelerator compilation |
0.8 | 1 | 2024 | Invited: New Solutions on LLM Acceleration, Optimization, and Application · DAC 2024 |
Electronic design automation
hardware/software co-design |
0.8 | 1 | 2024 | Invited: New Solutions on LLM Acceleration, Optimization, and Application · DAC 2024 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › transformer accelerator
large language model accelerator |
0.8 | 1 | 2024 | Invited: New Solutions on LLM Acceleration, Optimization, and Application · DAC 2024 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.8 | 1 | 2024 | Invited: New Solutions on LLM Acceleration, Optimization, and Application · DAC 2024 |
Electronic design automation
hardware verification and test |
0.2 | 1 | 2024 | Invited: New Solutions on LLM Acceleration, Optimization, and Application · DAC 2024 |
Electronic design automation › hardware verification and test › hardware verification
high-level synthesis verification |
0.2 | 1 | 2024 | Invited: New Solutions on LLM Acceleration, Optimization, and Application · DAC 2024 |
Methods — techniques the papers use, named apart from their topics
high-level synthesis · 1.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification
Lily Jiaxin Wan, Chia-Tung Ho, Yunsheng Bai, Cunxi Yu, Deming Chen, Haoxing Ren |
VTS | 1 |
| 2025 | PREFACE - A Reinforcement Learning Framework for Code Verification via LLM Prompt Repair
Manvi Jha, Lily Jiaxin Wan, Huan Zhang 0001, Deming Chen |
ACM Great Lakes Symposium on VLSI | 2 |
| 2024 | Invited Paper: Software/Hardware Co-design for LLM and Its Application for Design VerificationabstractThe widespread adoption of Large Language Models (LLMs) is impeded by their demanding compute and memory resources. The first task of this paper is to explore optimization strategies to expedite LLMs, including quantization, pruning, and operation-level optimizations. One unique direction is to optimize LLM inference through novel software/hardware co-design methods. Given the accelerated LLMs, the second task of this paper is to study LLMs’ performance in the usage scenario of circuit design and verification. Specifically, we place a particular emphasis on functional verification. Through automated prompt engineering, we harness the capabilities of the established LLM, GPT-4, to generate High-Level Synthesis (HLS) designs with predefined errors based on 11 open-source synthesizable HLS benchmark suites. This dataset is a comprehensive collection of over 1000 function-level designs, and each of which is afflicted with up to 45 distinct combinations of defects injected into the source code. This dataset, named Chrysalis, expands upon what’s available in current HLS error models, offering a rich resource for training to improve how LLMs debug code. The dataset can be accessed at: https://github.com/UIUC-ChenLab/Chrysalis-HLS. Lily Jiaxin Wan, Yingbing Huang, Hanchen Ye, Xiaofan Zhang 0001, Deming Chen |
ASPDAC | 1 |
| 2024 | Invited: New Solutions on LLM Acceleration, Optimization, and ApplicationabstractLarge Language Models (LLMs) have revolutionized a wide range of applications with their strong human-like understanding and creativity. Due to the continuously growing model size and complexity, LLM training and deployment have shown significant challenges, which often results in extremely high computational and storage costs and energy consumption. In this paper, we discuss the recent advancements and research directions on (1) LLM algorithm-level acceleration, (2) LLM-hardware co-design for improved system efficiency, (3) LLM-to-accelerator compilation for customized LLM accelerators, and (4) LLM-aided design for HLS (High-Level Synthesis) functional verification. For each aspect, we present the background study, our proposed solutions, and future directions. An extended version of this work can be found at: https://arxiv.org/abs/2406.10903. Yingbing Huang, Lily Jiaxin Wan, Hanchen Ye, Manvi Jha, Xiaofan Zhang 0001, Deming Chen |
DAC | 2 |