Recent studies indicate that resource-efficient online fault detection in dependable computing systems may rely on probabilistic data structures such as Bloom and Cuckoo filters. To be effective and lightweight, these filters require low-latency and resource-efficient hash-to-index mappings. Existing approaches, namely, modulo, power-of-two, and multiplicative indexing, either incur high implementation cost, latency overhead, or impose rigid table size constraints that can lead to over-provisioning and suboptimal memory utilization, limiting their adoption in embedded and real-time systems. To address these limitations, this work proposes a hardware-efficient hash-to-index reduction technique based on rejection sampling. The proposed method optimizes index computation, yielding a uniform distribution for arbitrary table lengths while avoiding costly division or multiplication. Implemented as a mask-then-reject datapath on FPGA, our approach enables lightweight online checkers that maintain low area and latency footprints without sacrificing correctness. Experimental results on Bloom and Cuckoo filters demonstrate similar detection accuracy compared to canonical mappings while reducing hardware cost and latency.

Racetrack memories (RTMs) have been shown to have lower leakage power and higher density compared to traditional DRAM/SRAM technologies. However, their efficiency is often hindered by the need to shift the targeted data to access ports for read and write operations. Suitable mapping approaches are therefore essential to unleash their potential. In this work, we explore the mapping of the popular tree-based document ranking algorithm, Quickscorer, onto Skyrmion-based racetrack memories (SK-RTMs). Our approach leverages a Logic-in-Memory (LiM) accelerator, specifically designed to execute simple logic operations directly within SK-RTMs, enabling an efficient mapping of Quickscorer by exploiting its bitvector representation and inter-leaved traversal scheme of tree structures through bitwise logical operations. We present several mapping strategies, including one based on a quadratic assignment problem (QAP) optimization algorithm for optimal data placement of Quickscorer onto the racetracks. Our results demonstrate a significant reduction in read and write operations and, in certain cases, a decrease in the time spent shifting data during Quickscorer inference.

As memory cells continue to shrink in modern semiconductor technologies, radiation-induced Single Event Effects, such as single- and multi-bit upsets, pose growing challenges to system reliability. While effective and efficient for single and double-bit errors, traditional error detection and correction approaches, such as Error Correcting Codes (ECC), incur substantial overhead and complexity when designed to detect and correct multiple-bit errors. This study investigates the use of probabilistic data structures (PDS) as lightweight detectors for multiple-bit soft errors in memories. Leveraging the space-efficient and low-latency properties of Bloom filters, we implement a lightweight error detector (checker) within a representative memory subsystem on a flash-based FPGA. The checker's performance is validated through extensive neutron beam irradiation and fault-injection campaigns, demonstrating effective detection of multiple-bit errors with a tunable false-positive rate.

High-criticality applications are vulnerable to Single Event Effects (SEEs) and require highly reliable and customizable microprocessors. Online checkers have been used to detect security and reliability issues in such systems. Popular hardware redundancy techniques such as Triple Modular Redundancy (TMR) and Dual Modular Redundancy (DMR) provide a high error coverage at the cost of substantial redundancy; therefore, there is an interest in introducing lightweight checkers that could offer the same detection ability as DMR with a much lower overhead. A possible implementation of these online checkers can be based on Probabilistic Data Structure (PDS) such as the Bloom Filter (BF). They are a form of information redundancy and an excellent complement to Single Error Correction Double Error Detection (SECDED) codes because they allow for detecting higher-order upsets. In this work, we integrate an online checker into the open-source RISC-V core NEORV32 and deploy it on a flash-based FPGA. This paper presents the evaluation of the online checker’s performance conducted under a neutron beam. The neutron beam experiments demonstrate that the real-life error rates of such structures are comparably worse than the initial simulation would indicate and that other factors can impact their performance.