Leena Elzeiny

dblp:383/8045 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2025
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
1 paper
Generative modeling · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Machine learning › Generative modeling
diffusion model
0.912025
Chip Placement with Diffusion Models · ICML 2025
Machine learning › Generative modeling › diffusion model
guided sampling
0.912025
Chip Placement with Diffusion Models · ICML 2025
Electronic design automation › physical design › placement › module placement
macro placement
0.912025
Chip Placement with Diffusion Models · ICML 2025
Electronic design automation
physical design
0.912025
Chip Placement with Diffusion Models · ICML 2025

Methods — techniques the papers use, named apart from their topics

synthetic dataset generation · 1.7diffusion model · 1.7
YearPublicationVenuePosition
2025 Chip Placement with Diffusion Models
abstract
Macro placement is a vital step in digital circuit design that defines the physical location of large collections of components, known as macros, on a 2D chip. Because key performance metrics of the chip are determined by the placement, optimizing it is crucial. Existing learning-based methods typically fall short because of their reliance on reinforcement learning (RL), which is slow and struggles to generalize, requiring online training on each new circuit. Instead, we train a diffusion model capable of placing new circuits zero-shot, using guided sampling in lieu of RL to optimize placement quality. To enable such models to train at scale, we designed a capable yet efficient architecture for the denoising model, and propose a novel algorithm to generate large synthetic datasets for pre-training. To allow zero-shot transfer to real circuits, we empirically study the design decisions of our dataset generation algorithm, and identify several key factors enabling generalization. When trained on our synthetic data, our models generate high-quality placements on unseen, realistic circuits, achieving competitive performance on placement benchmarks compared to state-of-the-art methods.
Vint Lee, Leena Elzeiny, Chun Deng, Pieter Abbeel, John Wawrzynek
ICML3