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Asal Mehradfar

dblp:383/8830 · DBLP profile ↗
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3ranked-venue papers
1as first author
3since 2021 · last 2026
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021Systems, architecture and hardware · 1 · 1 since 2021Security and privacy · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 80% Integrated circuit design · 20%
Artificial intelligence
1 paper
Graph learning · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits
0.912025
FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design · NeurIPS 2025
Electronic design automation
analog circuit design automation
0.912025
FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design · NeurIPS 2025
Electronic design automation
analog circuit synthesis
0.912025
FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design · NeurIPS 2025
Electronic design automation › logic synthesis
performance-driven synthesis
0.912025
FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design · NeurIPS 2025
Electronic design automation › analog circuit design automation
topology selection
0.912025
FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design · NeurIPS 2025
Machine learning › Graph learning
graph neural network
0.312025
FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design · NeurIPS 2025

Methods — techniques the papers use, named apart from their topics

performance-driven classifier · 1.7graph neural network · 1.7gradient-based parameter inference · 1.7
YearPublicationVenuePosition
2026 EM-Aware Physical Synthesis: Neural Inductor Modeling and Intelligent Placement & Routing for RF Circuits
Yilun Huang 0006, Asal Mehradfar, Amir Salman Avestimehr, Hamidreza Aghasi
ISCAS2
2025 CryptoMamba: Leveraging State Space Models for Accurate Bitcoin Price Prediction
Mohammad Shahab Sepehri, Asal Mehradfar, Mahdi Soltanolkotabi, Amir Salman Avestimehr
ICBC2
2025 FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design
abstract
Designing analog circuits from performance specifications is a complex, multi-stage process encompassing topology selection, parameter inference, and layout feasibility. We introduce FALCON, a unified machine learning framework that enables fully automated, specification-driven analog circuit synthesis through topology selection and layout-constrained optimization. Given a target performance, FALCON first selects an appropriate circuit topology using a performance-driven classifier guided by human design heuristics. Next, it employs a custom, edge-centric graph neural network trained to map circuit topology and parameters to performance, enabling gradient-based parameter inference through the learned forward model. This inference is guided by a differentiable layout cost, derived from analytical equations capturing parasitic and frequency-dependent effects, and constrained by design rules. We train and evaluate FALCON on a large-scale custom dataset of 1M analog mm-wave circuits, generated and simulated using Cadence Spectre across 20 expert-designed topologies. Through this evaluation, FALCON demonstrates >99\% accuracy in topology inference, <10\% relative error in performance prediction, and efficient layout-aware design that completes in under 1 second per instance. Together, these results position FALCON as a practical and extensible foundation model for end-to-end analog circuit design automation.
Asal Mehradfar, Xuzhe Zhao, Yilun Huang 0006, Emir Ceyani, Yankai Yang, Shihao Han, Hamidreza Aghasi, Amir Salman Avestimehr
NeurIPS1