Multi-objective design space exploration (DSE) for complex high-performance CPUs presents a significant challenge due to extensive parameter ranges and the vastness of the design space. Prior works either overlook microarchitectural information during DSE or necessitate intricate analysis for power, performance and area (PPA) evaluations. In this work, we present a novel DSE methodology for CPUs, which leverages large language models (LLMs) as an assistive tool to accelerate and automate the DSE flow. We develop an LLM-aided architecture-oriented DSE framework, i.e., Chat-A2, with satisfactory effectiveness and flexibility. Chat- $\mathbf{A}^{\mathbf{2}}$ is able to quickly explore 98% of the Pareto hyper-volume covered by the real Pareto optimal set without utilizing pre-sampled datasets or complex, customized analytical mechanisms. Experiments on an open-source high-performance RISC-V XiangShan CPU conclude that Chat-A ${ }^{\mathbf{2}}$ can obtain up to 19% normalized performance improvement while achieving 21.3% normalized area reduction compared to the default architecture optimized by professional human architects.

In large-scale distributed LLM training, communication between devices becomes the key performance bottleneck. Chiplet technology can integrate multiple dies into a package to scale-up node performance with higher bandwidth. Meanwhile, optical interconnect (OI) technology offers long-reach, high-bandwidth links, making it well suited for scale-out networks. The combination of these two technologies has the potential to overcome communication bottlenecks within and across packages. In this work, we present ChipLight, a cross-layer multi-objective design and optimization method for training clusters leveraging chiplet and OI. We first abstract an architecture model for such complex clusters, co-optimizing chiplet architecture, training parallel strategy, and OI network topology. Based on such models, we tailor the design space exploration flow by combining both black-box and white-box methodologies. Evaluated by our experimental results, ChipLight achieves significantly improved training efficiency and provides valuable design insights for the development of future training clusters.

Emerging multimodal LLMs (MLLMs) exhibit strong cross-modality perception and reasoning capabilities and hold great potential for various applications at edge. However, MLLMs typically consist of a compute-intensive modality encoder and a memory-bound LLM decoder, leading to distinct bottlenecks for hardware designs. In this work, we present a multi-core CPU solution with heterogeneous AI extensions, which are based on either the compute-centric systolic array or memory-centric digital compute-in-memory (CIM) coprocessors. In addition, dynamic activation-aware weight pruning and bandwidth management are developed to enhance bandwidth efficiency and core utilization, improving overall performance. We implemented our solution using commercial 22nm technology. For representative MLLMs, our evaluations show EdgeMM can achieve $2.84 \times$ performance speedup compared to laptop 3060 GPU.