VLDB 2026 Research / reviewers in the wild / expert
Haoyan Huang
dblp:389/0182
· DBLP profile ↗
3ranked-venue papers
0as first author
3since 2021 · last 2025
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 since 2021Security and privacy · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 56% Hardware accelerators and domain-specific architectures · 44% | |
| Databases, data mining, and information retrieval
1 paper |
Recommender systems · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Recommender systems › representation learning for recommendation
embedding-based recommendation |
0.8 | 1 | 2024 | Towards Redundancy-Free Recommendation Model Training via Reusable-aware Near-Memory Processing · DAC 2024 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
embedding layer acceleration |
0.8 | 1 | 2024 | Towards Redundancy-Free Recommendation Model Training via Reusable-aware Near-Memory Processing · DAC 2024 |
Memory systems › processing-in-memory
near-memory processing |
0.8 | 1 | 2024 | Towards Redundancy-Free Recommendation Model Training via Reusable-aware Near-Memory Processing · DAC 2024 |
Memory systems
processing-in-memory |
0.2 | 1 | 2024 | Towards Redundancy-Free Recommendation Model Training via Reusable-aware Near-Memory Processing · DAC 2024 |
Methods — techniques the papers use, named apart from their topics
reusable data identification · 1.5near-memory architecture · 1.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Blockchain-Verified Attribute-Based Keyword Search with User-Generated Keys in Multi-owner Setting for IoTabstractWith the rapid advancement of Internet of Things (IoT) technology, the security and utilization of data outsourced to the cloud is a prerequisite for IoT application in actual production. Attribute-based keyword search (ABKS) has emerged as a powerful primitive for fine-grained search over encrypted data for IoT. While recent advanced ABKS schemes support more abundant functions and query structures, they do not consider multi-owner setting. Moreover, these schemes typically rely on a single trusted attribute authority for user certificate verification and private key distribution. This centralization creates a single point of failure and raises security concerns, such as key escrow. Furthermore, the existence of malicious entities necessitates verification mechanisms. However, most existing approaches introduce unvetted third-party validators, leading to reliability issues and privacy risks. Nevertheless, in numerous schemes, malicious entities persist in operational status, thereby compromising systemic security. To address these challenges, we propose ABKS with user-generated keys (ABKS-UGK), which decentralizes key generation to individual data users, fundamentally resolving the key escrow vulnerabilities in traditional schemes. It not only leverages blockchain’s immutability for secure result verification, but also incorporates a revocation mechanism against malicious entities. Extensive experimental evaluations demonstrate its efficiency and reliability, making it suitable for secure, verifiable data sharing in real world. Zongmin Wang, Qiang Wang 0005, Fucai Zhou, Bao Li 0005, Jian Xu 0004, Haoyan Huang |
TrustCom | 6 |
| 2024 | Towards Redundancy-Free Recommendation Model Training via Reusable-aware Near-Memory ProcessingabstractThe memory-intensive embedding layer in recommendation model continues to be the performance bottleneck. While prior works have attempted to improve the embedding layer performance by exploiting the data locality to cache the frequently accessed embedding vectors and their partial sums. However, these solutions rely on the static cache, which is inapplicable in the embedding training scenario where the embedding vectors are updated frequently. To this end, this paper proposes ReFree, a redundancy-free near-memory processing (NMP) solution for recommendation model training. Specifically, ReFree identifies the reusable data in realtime for both embedding layer forward and backward stages and leverages a lightweight NMP architecture to enable redundancy-free near-memory acceleration of the entire embedding training process. Evaluation results on real-world datasets show that ReFree outperforms the state-of-the-art solutions by 10.9× and reduces 5.3× energy consumption on average. Haifeng Liu 0003, Long Zheng 0003, Yu Huang 0013, Haoyan Huang, Xiaofei Liao, Hai Jin 0001 |
DAC | 4 |
| 2024 | L-FNNG: Accelerating Large-Scale KNN Graph Construction on CPU-FPGA Heterogeneous PlatformabstractDue to the high complexity of constructing exact k -nearest neighbor graphs, approximate construction has become a popular research topic. The NN-Descent algorithm is one of the representative in-memory algorithms. To effectively handle large datasets, existing state-of-the-art solutions combine the divide-and-conquer approach and the NN-Descent algorithm, where large datasets are divided into multiple partitions, and a subgraph is constructed for each partition before all the subgraphs are merged, reducing the memory pressure significantly. However, such solutions fail to address inefficiencies in large-scale k -nearest neighbor graph construction. In this paper, we propose L-FNNG, a novel solution for accelerating large-scale k -nearest neighbor graph construction on CPU-FPGA heterogeneous platform. The CPU is responsible for dividing data and determining the order of partition processing, while the FPGA executes all construction tasks to utilize the acceleration capability fully. To accelerate the execution of construction tasks, we design an efficient FPGA accelerator, which includes the Block-based Scheduling (BS) and Useless Computation Aborting (UCA) techniques to address the problems of memory access and computation in the NN-Descent algorithm. We also propose an efficient scheduling strategy that includes a KD-tree-based data partitioning method and a hierarchical processing method to address scheduling inefficiency. We evaluate L-FNNG on a Xilinx Alveo U280 board hosted by a 64-core Xeon server. On multiple large-scale datasets, L-FNNG achieves, on average, 2.3× construction speedup over the state-of-the-art GPU-based solution. Chaoqiang Liu, Xiaofei Liao, Long Zheng 0003, Yu Huang 0013, Haifeng Liu 0003, Yi Zhang 0191, Haiheng He, Haoyan Huang, Hai Jin 0001 |
ACM Trans. Reconfigurable Technol. Syst. | 8 |