Demo Data from VLDB 2026 / reviewers in the wild / expert
Bhargava Nadendla
dblp:389/0433
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2024
0000-0003-0489-3005ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 50% Hardware accelerators and domain-specific architectures · 50% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › digital circuit design
arithmetic circuit design |
0.8 | 1 | 2024 | Fixed-point Encoding and Architecture Exploration for Residue Number Systems · ACM Trans. Archit. Code Optim. 2024 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.8 | 1 | 2024 | Fixed-point Encoding and Architecture Exploration for Residue Number Systems · ACM Trans. Archit. Code Optim. 2024 |
Hardware accelerators and domain-specific architectures › sparse matrix multiplication accelerator
matrix multiplication accelerator |
0.8 | 1 | 2024 | Fixed-point Encoding and Architecture Exploration for Residue Number Systems · ACM Trans. Archit. Code Optim. 2024 |
Integrated circuit design
residue number system arithmetic |
0.8 | 1 | 2024 | Fixed-point Encoding and Architecture Exploration for Residue Number Systems · ACM Trans. Archit. Code Optim. 2024 |
Methods — techniques the papers use, named apart from their topics
scaling-down postprocessing multiplication · 0.8redundant residue number system · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | Fixed-point Encoding and Architecture Exploration for Residue Number SystemsabstractResidue Number Systems (RNS) demonstrate the fascinating potential to serve integer addition/ multiplication-intensive applications. The complexity of Artificial Intelligence (AI) models has grown enormously in recent years. From a computer system’s perspective, ensuring the training of these large-scale AI models within an adequate time and energy consumption has become a big concern. Matrix multiplication is a dominant subroutine in many prevailing AI models, with an addition/multiplication-intensive attribute. However, the data type of matrix multiplication within machine learning training typically requires real numbers, which indicates that RNS benefits for integer applications cannot be directly gained by AI training. The state-of-the-art RNS real-number encodings, including floating-point and fixed-point, have defects and can be further enhanced. To transform default RNS benefits to the efficiency of large-scale AI training, we propose a low-cost and high-accuracy RNS fixed-point representation: Single RNS Logical Partition (S-RNS-Logic-P) representation with Scaling-down Postprocessing Multiplication (SD-Post-Mul) . Moreover, we extend the implementation details of the other two RNS fixed-point methods: Double RNS Concatenation and S-RNS-Logic-P representation with Scaling-down Preprocessing Multiplication . We also design the architectures of these three fixed-point multipliers. In empirical experiments, our S-RNS-Logic-P representation with SD-Post-Mul method achieves less latency and energy overhead while maintaining good accuracy. Furthermore, this method can easily extend to the Redundant Residue Number System to raise the efficiency of error-tolerant domains, such as improving the error correction efficiency of quantum computing. Bobin Deng, Bhargava Nadendla, Kun Suo, Chloe Yixin Xie, Dan Chia-Tien Lo |
ACM Trans. Archit. Code Optim. | 2 |