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Hongpei Zheng

dblp:389/7045 · DBLP profile ↗
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3ranked-venue papers
0as first author
3since 2021 · last 2026
0009-0009-3657-6443ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
2 papers
Hardware security and side channels · 70% Systems and software security · 30%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 100%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels
microarchitectural side channel
1.012026
SSBleed: Non-Speculative Side-Channel Attacks via Speculative Store Bypass on Armv9 CPUs · HPCA 2026
Processor architecture and microarchitecture
speculative execution
1.012026
SSBleed: Non-Speculative Side-Channel Attacks via Speculative Store Bypass on Armv9 CPUs · HPCA 2026
Systems and software security
exploitation
0.812024
Whisper: Timing the Transient Execution to Leak Secrets and Break KASLR · DAC 2024
Systems and software security › exploitation
KASLR bypass
0.812024
Whisper: Timing the Transient Execution to Leak Secrets and Break KASLR · DAC 2024
Hardware security and side channels
side-channel attack
0.812024
Whisper: Timing the Transient Execution to Leak Secrets and Break KASLR · DAC 2024
Hardware security and side channels › side-channel attack
timing side channel
0.812024
Whisper: Timing the Transient Execution to Leak Secrets and Break KASLR · DAC 2024
Hardware security and side channels › microarchitectural attacks
transient execution attack
0.812024
Whisper: Timing the Transient Execution to Leak Secrets and Break KASLR · DAC 2024
Hardware security and side channels
side-channel countermeasures
0.312026
SSBleed: Non-Speculative Side-Channel Attacks via Speculative Store Bypass on Armv9 CPUs · HPCA 2026
Processor architecture and microarchitecture › speculative execution
transient execution
0.212024
Whisper: Timing the Transient Execution to Leak Secrets and Break KASLR · DAC 2024

Methods — techniques the papers use, named apart from their topics

reverse engineering · 2.0kernel patch · 2.0performance monitor unit · 1.5architectural timing analysis · 1.5
YearPublicationVenuePosition
2026 SSBleed: Non-Speculative Side-Channel Attacks via Speculative Store Bypass on Armv9 CPUs
abstract
Modern CPUs employ Speculative Store Bypass (SSB) to reduce load latency and improve performance. In response to transient attacks such as Spectre, CPU vendors have also introduced mitigations to prevent incorrect speculation from leaking data. In this work, we show that the SSB on Armv9 CPUs introduces a previously unexplored form of non-speculative data leakage. Specifically, we find that the SSB on Armv9 performance cores is governed by an undocumented predictor. Through reverse engineering, we uncover the design of this predictor and show that it lacks isolation across security domains. Furthermore, existing mitigations such as SSBS are insufficient to prevent leaks. Based on this, we present SSBleed, the first non-speculative side-channel attack via SSB on Armv9 CPUs. We validate the practicality of SSBleed through five case studies, including crossprocess RSA signature and key generation attacks on the latest version of MbedTLS and WolfSSL, interrupt detection, and improved data transmission in two transient attacks. Finally, we propose a flush-based mitigation through a kernel patch, which incurs an average performance overhead of 0.46 %.
Chang Liu 0117, Hongpei Zheng, Xin Zhang 0110, Dapeng Ju, Dongsheng Wang 0002, Yinqian Zhang, Trevor E. Carlson
HPCA2
2025 PointGS: Point-Wise Feature-Aware Gaussian Splatting for Sparse View Synthesis
Lintao Xiang, Hongpei Zheng, Qijun Yang, Hujun Yin
IET Image Process.2
2024 Whisper: Timing the Transient Execution to Leak Secrets and Break KASLR
abstract
The vulnerabilities of transient execution have been exploited in many side-channel attacks (SCA). We report Whisper, a novel transient execution timing (TET) side channel, which is based on the execution time difference of transient execution under different conditions. We develop TET version of SCAs including Meltdown, Zombieload, and Spectre-RSB that use Whisper as covert channel to leak information. We further propose TET-KASLR to break the kernel address space layout randomization (KASLR) mechanism under the protection of KPTI and FLARE. These attacks are simple to implement and can bypass the existing mitigation methods because the TET side channel relies on execution time that can be conveniently obtained by architectural level timing analysis. We demonstrate the correctness and effectiveness of these attacks on various x86-64 CPUs. The root cause of Whisper is analyzed with our toolset built on performance monitor unit (PMU) and potential defense against Whisper is also discussed.
Yu Jin 0010, Chunlu Wang, Pengfei Qiu, Chang Liu 0117, Hongpei Zheng, Yongqiang Lyu 0001, Xiaoyong Li 0003, Gang Qu 0001, Dongsheng Wang 0002
DAC6